Zhuhai Silicon Core Technology Co., Ltd. (referred to as "Silicon Core Technology") is mainly engaged in the R&D and industrialization of next-generation 2.5D/3D stacked chip EDA software design. The founding team has been researching 2.5D/3D chip design methods since 2008 and is one of the earliest research teams in the industry to study cutting-edge chip architecture design methods. Achieving chip systems with higher performance, higher integration, higher reliability, and lower power consumption through stacked chip design can not only bridge the gap in domestic chip EDA software but also leverage the industry trend of 2.5D/3D stacked chips to help upgrade and iterate the design of various types of domestic chips, promoting the development of RISC-V, AI (Artificial Intelligence), GPU, CPU, NPU, and other chips and terminal application fields.
Editor's Note
AI computing power demand continues to surge, posing higher requirements for chip performance. Against the backdrop of restricted advanced process nodes, technologies such as 2.5D/3D stacking, Advanced Packaging, and Chiplet integration are rising rapidly, becoming the mainstream path to break through the upper limit of chip performance and achieve computing power upgrades, which has also pushed supporting EDA tools to the forefront of the industry. In this issue, we interview Wu Minghui, Senior Product R&D Engineer at Silicon Core Technology, to dissect the difficulties in the industrialization of the 2.5D/3D stacked chip EDA track and the long-term prospects of industrial development, and to explore the differentiated breakthrough path for the new generation of domestic 3D stacked chip EDA.
Welcome to the Interview Podcast
*The following is the text transcript of the podcast, confirmed and authorized by the guest.
Reconstructing the Starting Point: Breaking Free from the 30-Year Generational Gap in EDA
Huanshi: The Advanced Packaging track is currently highly popular, and industry attention continues to rise. The product direction researched by Silicon Core Technology is also very unique. Could you first introduce your company's main products and business segments?
Wu Minghui: Silicon Core Technology is a company focused on the R&D of 2.5D/3D stacked chip EDA tools, and also one of the few core enterprises in China that currently possesses full-process stacked chip design tools. We have independently developed the 2.5D/3D stacked chip EDA full-process platform—3Sheng Integration Platform, which covers five core segments: architecture design, physical design, test fault tolerance, analysis simulation, and multi-Chiplet verification.
3Sheng Integration Platform (Image source: Silicon Core Technology)
Huanshi: So you are a pure software EDA company, right?
Wu Minghui: Yes, our core products are 2.5D/3D stacked chip EDA design tools targeting Advanced Packaging technology.
Huanshi: From the laboratory to industrial implementation of 2.5D/3D stacking technology, what are the common bottlenecks in the industry? As a company that laid out this field early, you should have a deeper feeling about this.
Wu Minghui: Our founding team is indeed among the first batch of R&D personnel globally. We started developing 2.5D/3D chip stacking tools in 2008. The main difficulties we encountered lie in technology implementation and supply chain collaboration. On the one hand, theoretical technology needs to be transformed into standardized commercial tools; on the other hand, the collaborative link between chip design companies and packaging and testing factories must be opened up to promote the industry chain's recognition of domestic stacked chip EDA solutions.
Huanshi: Judging from this, the industry still needs to do a lot of market education work?
Wu Minghui: Yes. Advanced Packaging is a clear transformation direction for the semiconductor industry, but most domestic chip design companies lack 2.5D/3D stacking development experience. Therefore, most of the time, we are not just tool suppliers, but also provide supporting design services to assist customers in implementing multi-chip stacking solutions.
Huanshi: Without professional stacking design tools, how can enterprises achieve multi-chip integration with traditional solutions? Does stacking technology belong to process iteration and upgrade, or does it completely replace the original solutions?
Wu Minghui: It belongs to industrial technology upgrade, rather than replacing the original single-chip route. Currently, AI and high-computing-power chips face problems such as restricted advanced process nodes and barriers to domestic process nodes. 2.5D/3D stacking is the core technical path for domestic breakthroughs in computing power bottlenecks. Even overseas giants such as Intel, AMD, and NVIDIA, which have mastered advanced process nodes, are also adopting stacking solutions on a large scale.
If domestic stacked EDA tools are lacking, domestic enterprises can only purchase licenses from overseas manufacturers. Not only are the licensing fees high, but there is also a risk of leakage of core design data, and the supporting functions for high-end advanced processes will also be restricted.
Huanshi: What is the technological gap between domestic and foreign manufacturers?
Wu Minghui: Currently, there are three major mainstream international suppliers: Synopsys, Cadence, and Siemens EDA. They started laying out 2.5D/3D IC stacking tools around 2010, while our team started relevant R&D in 2008. We are the first batch of R&D teams in China to tackle this field, and we are almost on the same starting line as overseas manufacturers.
Huanshi: That is to say, in the 2.5D/3D stacked EDA track, we do not lack technological accumulation, unlike the huge difficulty in catching up in the traditional silicon-based 2D EDA.
Wu Minghui: Yes. Traditional 2D EDA tools have a generational gap of nearly 30 years with overseas counterparts. Even if we keep updating our own technology to catch up, it is difficult to achieve substitution.
System-Level Design: The Logical Switch from Single-Chip to Multi-Chip
Huanshi: I noticed that you proposed system-level collaborative optimization design. What is the difference between this model and the traditional chip R&D model? What kind of changes will it bring to the industry?
Wu Minghui: The host mentioned a very good term: system-level planning. In the single-chip era, the design process was relatively independent and simple, while 2.5D/3D stacking requires multiple dies to be interconnected through a silicon interposer. The electrical, thermal, and timing aspects between chips are coupled with each other. It must be planned uniformly from the perspective of the whole system to provide complete guidance for subsequent single-chip design and interconnection layout. This is also the core value of system-level collaborative design.
Huanshi: Will it be difficult for an EDA company to take the lead in building a full-system design process? What capability bottlenecks need to be broken through?
Wu Minghui: As the only company in China with a full-process stacked chip EDA toolchain, we are deeply aware of the characteristics of deep coupling between tools, design, and packaging and testing processes. In the process of tool R&D, we are deeply bound to leading domestic Advanced Packaging factories and 3D IC design teams. Taking EDA tools as the intermediate hub, we link upstream chip design companies and downstream packaging and testing production lines for collaborative development to jointly build and improve the system-level stacked chip design process.
Huanshi: Have you started direct bidding with international manufacturers at present?
Wu Minghui: There are export controls on advanced 3D IC design tools overseas. Not only is the procurement cost high, but the technology for high-end advanced process nodes is also not open to the domestic market. The supply in the domestic market is relatively blank, so there has been no large-scale direct bidding at this stage. In the future, after we expand into overseas markets, there will inevitably be competition with international manufacturers.
Huanshi: So looking at it the other way around, the current international landscape has actually left a development window period for companies like yours?
Wu Minghui: Yes, the current international landscape is a rare development window period for us, for two reasons:
First, there is no generational gap in time. Traditional EDA has been monopolized overseas for decades, and we cannot catch up; but 3D IC/Advanced Packaging is a brand-new track, and domestic and foreign players started almost at the same time, with no historical gap.
Second, we have a greater advantage on the demand side. China has the most active chip application market in the world and the most urgent demand for independent and controllable technology. Moreover, leading enterprises have a large number of real and complex stacked chip demands on the design side, forcing our EDA tools to iterate and polish quickly in actual combat. This pace of "large-scale application scenarios driving product maturity" is a condition that overseas manufacturers do not have. The more customers and the more complex the demands, the faster our tools progress—this is the window period for Silicon Core.
Huanshi: Could you share with us again the overall maturity of domestic customers in implementing 2.5D/3D stacked chip projects? What are the main scenarios for market demand?
Wu Minghui: Okay, I will answer from two aspects.
On the demand side, the demand for computing power in AI, embodied intelligence, and autonomous driving continues to explode. Chips such as CPU, GPU, and NPU are generally turning to stacked architectures, and market demand is rigid in the long term.
On the industry side, more and more chip design companies are starting to set up stacking R&D teams and launch project financing layouts. The overall development trend of the domestic Advanced Packaging industry is steadily improving.
Advanced Packaging 2.5D/3D Stacked Chip Design Services (Image source: Silicon Core Technology)
Huanshi: How is your current customer onboarding situation? Have you formed stable paying customers? What is the biggest challenge in commercial implementation?
Wu Minghui: At present, we already have a certain number of commercial orders and have reached project cooperation with leading domestic Advanced Packaging factories and mainstream chip design companies. Our commercialization path is relatively clear, and the development trend is steady.
The biggest challenge encountered is dispelling customers' trust concerns about domestic tools. Traditional 2D EDA has a generational gap of nearly 30 years between domestic and overseas, and the industry naturally has prejudice against domestic tools. But in the 2.5D/3D stacked chip EDA track, we are almost on the same starting line as overseas. We will fully demonstrate to customers our years of technological accumulation and the unique advantages brought by deep industrial collaboration. At present, we have gained the recognition of leading domestic Advanced Packaging factories and design companies.
Huanshi: Listening to your conversation, I feel that you are full of confidence in this track. Are there many domestic enterprises developing similar full-process stacked EDA tools?
Wu Minghui: Not many. There are less than 10 enterprises in China laying out stacking-related tools, and the vast majority only provide single-point tools; Silicon Core Technology is currently the only enterprise in China that can provide full-process 2.5D/3D stacked EDA tools (system architecture planning, physical design, multi-physics simulation, multi-die test fault tolerance, multi-Chiplet integration verification), and it is the leading enterprise that started the earliest and has the most complete full-process coverage in this segmented track.
Stacking is Not a Transition, but the Long-Term Answer for Computing Power Chips
Huanshi: Looking ahead to the next five to ten years, will 2.5D/3D stacking technology exist in the long term, or is it a phased transition solution? What is the prospect of the overall market space?
Wu Minghui: 3D stacking belongs to the long-term core solution. As the demand for AI computing power continues to expand, storage leaders such as Samsung are laying out stacked product routes around AI, and the global chip industry will evolve towards multi-chip stacking.
For the domestic industry, the development of advanced process nodes is restricted, and the progress of 5nm and 3nm chip process nodes is slow. Relying on mature processes combined with stacking technology to improve computing power is the most feasible technical route, and the market scale will continue to expand in the next ten years.
Huanshi: As a pioneer in the industry, if you were to share experience with peers in the track and new practitioners, what content would you focus on emphasizing?
Wu Minghui: First, they must thoroughly understand the underlying development logic of the semiconductor industry, understand the core drivers of the industry's shift from single-chip 2D design to 2.5D/3D multi-chip stacking, and the underlying logic of computing power demands in various application scenarios. Only by thoroughly understanding the context of industrial evolution can we find the right R&D direction for EDA tools, which is also the foundation for us to launch the new paradigm of STCO system-level collaborative design.
New Paradigm of STCO System-Level Collaborative Design (Image source: Silicon Core Technology)
Huanshi: Let me ask you a final rather challenging question. Why is it Silicon Core Technology that can provide customers with a complete domestic substitution solution?
Wu Minghui: The core confidence comes from long-term technological accumulation. In 2008, the founder of our team conducted research on 3D stacked chip design at the University of Southampton in the UK, under the guidance of a mentor who is a Fellow of the Royal Academy of Engineering. By 2026, we will have a technological accumulation of up to 18 years. The reason we started to enter this track so early is that we saw that the fundamental solution to improving chip computing power and extending Moore's Law is optimizing chip interconnection performance. High-density multi-chip interconnection requires a brand-new EDA toolchain to match Advanced Packaging processes. Therefore, we decided to deeply cultivate the technical direction of 3D stacking in the long term.
Huanshi: With a technological accumulation of up to 18 years, it belongs to a very senior R&D team in the industry. So I think the semiconductor industry is still full of surprises. In the traditional 2D EDA track, we may really not be able to outcompete others; but in emerging tracks like 3D stacking, we have achieved synchronous development.
Wu Minghui: Borrowing the case that Dr. Zhao Yi, our founder, always loves to mention, in the field of traditional fuel engines, China has been catching up with overseas for a long time, while in the new energy track, it can achieve synchronous competition; the same applies to 2.5D/3D stacking. By jumping out of the shackles of the generational gap in traditional 2D EDA, we can also achieve overtaking on the curve in the industry.
Huanshi: Okay, thank you Dr. Wu for today's sharing, which allows us to see how domestic EDA has walked out of a differentiated breakthrough path, and fully feel the vigorous innovation power of the domestic semiconductor industry.
Wu Minghui: Yes, after years of precipitation, the technological level of domestic Advanced Packaging processes has a very small generational gap with overseas, which also provides a good industrial soil for the new generation of domestic 2.5D/3D stacked chip EDA tools.
Huanshi: Thank you again Dr. Wu. I wish you and the company better and better development, and more customers for your product implementation.
Wu Minghui: Thank you, and thank the host for the blessings.
END
Interview | Huanshi Editor | Xiaoqie Review | Huanshi