Amid the dual technological evolution of high-voltage main drives in new energy vehicles and high-power-density AI computing power supplies, the competitive focus in the silicon carbide (SiC) power semiconductor sector has shifted from simple material substitution to deep integration of "process miniaturization—packaging thermal management—electronic control system integration."
At the 2026 Bay Area Semiconductor Industry Ecology Expo (WESEMiBAY), YASC disclosed the latest electrical data and process progress for its high-performance SiC MOS chips, PCB embedded packaging, and A3-level wafer fab, demonstrating an evolutionary path from chip-level optimization to system-level architecture definition.
Image source: YASC
From Planar Limits to Extreme Trenches
The strategic importance of SiC devices has become increasingly prominent in recent years. In previous planar device R&D, YASC successfully launched the fourth-generation PG4E, fifth-generation PG5E, and the latest sixth-generation PG6N planar chips by optimizing multi-stage P-well implantation and body doping distribution, continuously shrinking the specific on-resistance (Rsp) at 175°C to an industry-leading level of 3.2mΩ.cm².
A direct benefit of this technology iteration is a significant improvement in chip current output capability. Taking NEV main drives as an example, under identical packaging conditions, simply upgrading the chips within the module from PG4E to the high-performance PG5E increases the output current from 450Arms directly to 540Arms, achieving a 20% performance leap.
However, unit cell dimensions in planar devices face physical limits; once Rsp approaches 2.0mΩ.cm², further optimization space becomes extremely limited.
In response, Li Gang, Vice President of Strategic Operations Center at YASC, revealed that YASC began patenting trench-type MOSFETs in 2023 to pursue higher power density.
He pointed out that gate oxide breakdown and early failure caused by electric field line concentration have long been recognized common challenges in SiC trench device R&D. YASC's process innovation team introduced innovative "double-sided deep masking" and "double-sided deep burial" technologies, combined with refined trench bottom rounding processes, successfully reducing trench sidewall roughness (Ra) to 0.15nm, surpassing the 0.7nm level of industry competitors.
Meanwhile, the team created Buried P Shielding structures and high-mobility trench gate oxide processes, enabling the first-generation trench device TG1N and second-generation TG2N to significantly reduce on-resistance while exhibiting excellent short-circuit withstand capability and long-term electro-thermal reliability.
As of October 2025, YASC had publicly filed 79 global patents in this field, ranking third globally among industry peers, formally competing with international semiconductor giants at the forefront of advanced technology.
DeepXE™ Embedded Technology and Diffusion Bonding Process
While breakthroughs in chip manufacturing are crucial, maximizing the material advantages of silicon carbide requires systemic reconstruction of packaging technology. In the automotive-grade main drive market, traditional leadframe or plastic package production involves expensive equipment investment, lengthy BoM supply chains, and performance improvements that have hit bottlenecks. Against this backdrop, YASC launched its self-developed DeepXE™ power semiconductor PCB embedded technology.
Image source: YASC
According to YASC, this technology focuses on Cavity-Free AMB ceramic frame embedded units and relies on copper plating on chip top surfaces and multi-physics coupled 3D power path construction. The PCB embedded solution cleverly shifts the primary manufacturing phase to the mature PCB supply chain, avoiding the pain point of repeated mold opening for customization and achieving leading hardware specifications.
Demonstrated real-world data at the launch event showed that within an area the size of a deck of cards, the DeepXE™ solution can embed 24 SiC MOS chips and achieve peak energy conversion of 250kW. Compared to traditional packaging, volume and weight are reduced by 50%, overall switching losses are decreased by 20%, and stray inductance (Ls) is compressed to an extreme level below 0.9nH.
Simultaneously, addressing the pursuit of ultimate energy efficiency in large-scale AI data centers (AIDC) and solid-state transformers (SST), YASC launched the EZ family (EZ2C/EZ3C), China's first power modules adopting advanced diffusion bonding processes in the industrial segment.
According to descriptions, traditional solder sheet processes are prone to voiding and have low melting points under high temperatures and long-term service. In contrast, diffusion-bonded layers are dense and flat, improving bond strength by 2-3 times. This reduces the junction-to-case thermal resistance of EZ2C by 18%, lowers chip junction temperature by more than 25°C at full load, and effectively supports SiC operation at extreme temperatures above 200°C without interruption.
Furthermore, regarding circuit topology integration, the EZ3C features an innovative high-efficiency SHB three-level topology that pushes the power of a single SST module above 100kW, drastically reducing the cascade stages of a 10KV AI SST system from 16 to 8, substantially optimizing the topological complexity of high-voltage systems.
Flywheel Effect of the First A3-Level SiC Smart Wafer Fab
High yield and batch consistency are core thresholds for power semiconductors entering automotive and large-scale computing infrastructure. YASC established a fully automated smart SiC wafer manufacturing plant in Wuhan, being the first in China to implement an A3-level (fully automated manufacturing execution and dynamic optimization) AMHS overhead hoist transport and scheduling system.
Image source: YASC
Currently, the Wuhan base has achieved an A3 system automatic online rate of over 98% and a smart dispatch rate of over 90%.
In wafer yield engineering control, the factory independently developed a full-lifecycle yield traceability and product screening mechanism covering substrate, epitaxy, inline processes, wafer-level high-voltage testing, die testing, and known good die selection. Additionally, the system implements full digital mapping and statistical process control-based out-of-control action plans for dislocation defects (Downfall/Triangle/Micropipe Killer defects) and key layer defects (PW/GT).
Process statistics displayed by YASC indicate that this smart manufacturing system enables non-linear rapid yield ramp-up in the new plant. Currently, the CP yield for 5mm×5mm automotive-grade large-size dies has stabilized above 98%. Meanwhile, the tape-out import cycle for new products has seen a three-fold speed increase.
At the facility control level, through joint development of an AI smart facility control system with renowned universities, YASC utilizes data analysis, physical mechanism modeling, and multi-modal perception closed loops to achieve global smart variable frequency control of chillers, HVAC systems, and cleanroom FFUs, resulting in comprehensive operational energy savings exceeding 10.5% in the wafer fab.
Conclusion
As Li Gang stated during media interviews, the explosion of AI computing power in the digital world must ultimately land in the physical world to "do work" and drive various physical actions; and every instance of doing work in the physical world relies on precise driving by power chips.
Against this background, from automotive main drives to AI data centers, and from industrial energy to household appliances, YASC is rapidly expanding the application boundaries of silicon carbide technology relying on its self-developed dual-track planar and trench chips, along with the full matrix of DeepXE™ and EZ modules.