As Artificial Intelligence (AI) moves from cloud-based large models to physical-world applications such as automobiles and robots, the competitive logic for edge-side AI chips is evolving. For chips, AI computing power figures remain important but are no longer sufficient on their own to determine competitiveness. Taking intelligent driving as an example, whether large models can run efficiently on the vehicle side, whether chips can keep pace with the rapid evolution of model requirements, whether systems meet the stringent automotive demands for power consumption and safety, and whether products can achieve scalable mass production at reasonable costs are collectively determining the commercial prospects of chip companies.
On October 29, XHEART officially released the X7 Ultra, a vehicle-grade intelligent driving chip designed for end-to-end large models. The chip embodies the core philosophy of "defining chips by large models," designing its architecture based on real mass-production model needs, with a computing power of 700 TOPS. Meanwhile, XHEART announced the R&D targets for its next-generation chip, the X9: achieving 3,000 TOPS of large model computing power and 700 GB/s memory bandwidth per single chip.
Additionally, XHEART revealed that within eight months of mass production, the cumulative shipments of the X7 series have exceeded 200,000 units, deployed in 10 mass-produced vehicle models, and secured orders for over 40 vehicle models.
For a chip design company established only in 2023, progressing from startup to mass production, then to multi-model design-in and hundreds-of-thousands-level shipments, signifies crossing the most difficult commercialization threshold for初创 chip enterprises. However, in a market dominated by NVIDIA, Qualcomm, Horizon Robotics, and automakers' self-developed chips, if XHEART aims to expand its share starting from intelligent driving, it must answer a sharper question: When the industry is not lacking intelligent driving chips, why would OEMs need another option?
The answer from XHEART CEO Li Zonglin lies in the technology route locked in at the project's inception in 2023—"defining chips by large models." In his view, XHEART's differentiation stems from a deep understanding of large model computational characteristics, the ability to co-define chip architectures with algorithm trends, engineering discipline in mass production delivery, and a business model built around customer value.
I. Why "Define Chips by Large Models"?
To understand the product positioning of XHEART X7 Ultra, one must first look at the shifts in intelligent driving technology routes.
Li Zonglin, who has over 20 years of experience in chip design, recalled during the launch event that traditional intelligent driving systems typically split perception, prediction, and planning into different models, each completing corresponding tasks. While this architecture offers clear responsibilities, information transfer between different models can lead to loss of effective data and limit the system's overall generalization capability.
With the development of Transformer-based end-to-end large models, intelligent driving is shifting from relying on engineers pre-designing rules and multiple small models executing separate tasks, towards a more data-driven technical route. Models need to handle more complex scenarios and utilize more data to learn patterns in road environments.
This shift imposes new requirements on chips:
First, theoretical computing power does not equal effective computing power in real applications. TOPS, FPS, or model runtime obtained from laboratory tests do not necessarily represent the performance achieved by mass-production intelligent driving models on actual vehicles. Factors such as model structure, operator support, memory access, and task scheduling can all impact final execution efficiency.
Second, automotive chips face product cycles vastly different from algorithms. Li Zonglin pointed out in his speech that while fast model iterations may occur every six months, the vehicle development cycle typically spans 3 to5 years, and a car's usage lifecycle can reach 5 to 10 years.
This means that when a chip completes design and enters mass production, the initially adapted model may have undergone multiple iterations. If the chip architecture did not fully consider future model directions during the design phase, subsequent OTA upgrades could be constrained by computing power, memory bandwidth, or software toolchains.
Third, on-board computing power cannot ignore power consumption and cost constraints. Simply adding transistors and computing units can increase power, but automotive thermal conditions, chip area, and total vehicle cost have strict boundaries. How to fully leverage large model capabilities under limited resources is the true problem that vehicle-grade intelligent driving chips need to solve.
"We need to rethink how computation, storage, and data flow are organized starting from real large model needs, so that chip resources are truly used where the model requires them," Li Zonglin stated the core technical philosophy of XHEART at the launch event.
This is what is known as "defining chips by large models": rather than completing a generic chip architecture first and having algorithm teams adapt to it, model requirements are incorporated into the architecture definition process from the early stages of chip design, involving hardware-software co-design centered on model computational characteristics, data flow, storage needs, and future evolution directions.
Li Zonglin emphasized that this route is not deliberately pursuing differentiation for the sake of technical novelty, but aiming to solve problems in real applications. He believes chip manufacturers must choose between generality and specificity; the ultimate criterion is not how advanced the architecture sounds, but whether it creates actual value for customers. This also explains why XHEART chose to bet on end-to-end large models when it started up in 2023.
At that time, the capital market environment was not loose, and the application prospects of large models on the vehicle side were not as clear as they are today. For a chip design company requiring long-term massive investment, abandoning conventional low-risk generic computing architectures to preemptively choose a "defining chips by large models" technology route that had not been sufficiently validated meant bearing higher R&D and commercialization risks.
"We could only make one choice back then, and we only had one chance, but we firmly believed this route could provide immense value to users. Over these three years, our judgment on the trend of data-driven large models has indeed been verified," said Li Zonglin.
II. Trade-offs Behind 700 TOPS: Not Stacking Power, But Improving Efficiency
The large model computing power of the newly released X7 Ultra is 700 TOPS. Unlike simply emphasizing power figures, XHEART focused the launch event on large model execution efficiency.
According to Li Zonglin, the X7 Ultra adopts an ultra-large core NPU architecture and has specifically optimized key operators, data access paths, and the AI toolchain around the computational characteristics of Transformer models.
First, adopting an ultra-large core NPU + multi-level cache architecture reduces data movement during model execution.
Traditional small-core architectures enable parallel work through multiple computing units, but as end-to-end large model computations and data interactions become increasingly concentrated, data exchange between multiple computing units can bring additional overhead.
XHEART chose an ultra-large core NPU design, hoping to allow more tightly coupled computational tasks to be completed within more centralized computing units. Li Zonglin likened this in his speech to placing teams originally scattered across different offices, needing to repeatedly pass materials, into a workspace capable of efficient collaboration.
According to XHEART disclosures, data interaction between traditional small cores is on the order of hundreds of GB/s, while interconnection speeds within ultra-large cores reach TB/s levels. Combined with large-capacity, high-concurrency multi-level caches, the chip allows data required for computation to stay as close to the processing unit as possible, reducing waiting and movement.
Li Zonglin further explained that data movement not only impacts performance but also consumes significant power, increasing the thermal burden on domain controllers and the entire system. Therefore, chip design cannot just pursue the number of computing units but must also focus on where data comes from, which links it passes through, and how many times it ultimately needs to be moved.
Second, dedicated acceleration engines are designed for key operators of Transformer models.
As model architectures evolve from traditional convolutional networks to Transformers, some computational tasks place different requirements on chip operator support, data access efficiency, and execution precision.
The X7 Ultra designs dedicated hardware accelerators for critical computational steps like LayerNorm, Softmax, and Transpose, paired with efficient buffer registers, aiming to improve efficiency in both computation and data access.
This reflects XHEART's understanding of chip design: if key model calculations require frequent switching between different processing units or repeated access to external memory, even a chip with very high theoretical computing power may fail to fully unleash its performance.
By optimizing these high-frequency computational steps at the hardware architecture level, XHEART aims to reduce data movement and improve overall efficiency while ensuring model inference accuracy.
Third, integrating the AI toolchain into chip architecture design to achieve whole-network optimization.
Competition among large model chips occurs not only at the hardware level. How models are compiled, split, scheduled, and deployed also impacts actual performance.
Li Zonglin emphasized that the X7 Ultra underwent a deep reconstruction of its AI toolchain, expanding the optimization scope from local continuous operators to the entire network. By uniformly splitting, orchestrating, and merging computational tasks across different layers and branches, the toolchain reduces the process of repeatedly writing intermediate results to external memory and reading them back.
XHEART calls this capability "whole-network fusion" and states it enables zero-copy memory access for the entire network. The core here is not completely avoiding external memory access, but minimizing repeated read-writes of intermediate computational results, concentrating external memory access primarily on model inputs, outputs, and necessary weight loading.
This aligns with a point Li Zonglin repeatedly emphasizes: models are constantly evolving, so chips must possess highly efficient toolchains to ensure smooth deployment of subsequent model iterations onto existing hardware.
According to data disclosed by XHEART at the launch event, thanks to the hardware-software co-design of the X7 Ultra, the computational utilization rate of mass-production large models with Transformer architecture on its NPU reaches 98.7%; under conditions of comparable large model performance, compared to flagship industry products, the X7 Ultra reduces memory bandwidth consumption by 80% and improves inference energy efficiency by 100%.
Although the 700 TOPS computing power of the X7 Ultra is not aggressive among current domestic intelligent driving chips, XHEART attempts to prove that through innovative architecture and hardware-software synergy, the X7 Ultra can convert more computing power into actual model inference capability efficiently.
In simple terms, if a chip labeled with 700 TOPS has an actual utilization rate of only 60%, its effective computing power is around 420 TOPS; if the utilization rate approaches 99%, the gap in usable computing power under the same label widens significantly. More critically, an 80% reduction in bandwidth consumption implies a substantial decrease in reliance on DDR—against the backdrop of tight memory supply and price surges in 2026, this directly translates to controllability of domain controller BOM costs. Furthermore, frequent data movement not only drags down performance but also consumes power, increasing the thermal burden on the entire system. On the vehicle side, every increment in energy efficiency releases more available computing space.
For automakers, the value of the X7 Ultra's extreme efficiency will ultimately manifest in real-world scenarios: whether models can complete inference faster, whether judgments in complex road scenarios can be more stable, and whether larger models can enter more vehicle models while keeping power consumption and costs controllable.
III. Armv9 Vehicle-Grade CPU: More Than Just a "Scheduler" for the Chip
In the entire intelligent driving SoC, the NPU handles high-intensity AI computational tasks such as large model inference, but a chip does not operate efficiently solely by having a powerful NPU. Complex intelligent driving systems involve task scheduling, control logic, system coordination, and cooperation between different computing units. The role of the CPU is to provide processing capability for these general-purpose computing and control tasks and coordinate the operation of the entire chip.
Another major innovation in the X7 Ultra's architecture design is the debut adoption of an Armv9 vehicle-grade CPU in China, being the first to achieve mass production domestically. According to Li Zonglin's introduction at the launch event, the Armv9 vehicle-grade CPU used in the X7 series entered mass production with customer vehicle models in March2026.
Li Zonglin described the CPU as the "super scheduler" within the entire chip. The goal is for the CPU to maintain agility while possessing sufficient capability to handle complex control and system coordination tasks. In other words, the X7 Ultra is not simply stacking NPU computing power but attempting to let the CPU, NPU, and other specialized computing units perform their respective duties, avoiding cramming all tasks onto the same type of processor.
It is reported that compared to the previous generation, the Armv9 vehicle-grade CPU used in the X7 series sees a 20% improvement in performance and a 10% improvement in energy efficiency. Additionally, the CPU adopts a new SVE2 vector processing engine, offering stronger DSP performance compared to the previous generation's NEON vector processing capability; the large cluster architecture further improves multi-core coordination and L3 cache access efficiency.
The significance of these improvements is not for the CPU to replace the NPU in executing main large model computations, but to enhance the CPU's own task processing efficiency, improve coordination between multi-cores, and optimize data access performance. For an automotive SoC composed of multiple computing units, the CPU's processing capability, cache access efficiency, and system scheduling efficiency also affect whether various tasks can connect smoothly.
This constitutes the other side of the X7 Ultra's "hardware-software synergy" route: on one hand, improving large model computational efficiency through ultra-large core NPUs and dedicated acceleration engines; on the other hand, enhancing control, scheduling, and multi-core coordination capabilities via the Armv9 vehicle-grade CPU, with the software toolchain organizing the entire computing process. Its goal is not to have one processor bear all tasks, but to enable different computing units to collaborate in more appropriate ways.
IV. From Chip Mass Production to Vehicle Delivery: XHEART's Engineering Test
For vehicle-grade chips, designing a chip with excellent performance is only part of the entire product cycle. Every step from tape-out, return, hardware-software integration, to domain controller adaptation, full-vehicle validation, and scale mass production can become a bottleneck for commercialization. The mass production progress of the previous generation X7 series chips disclosed by XHEART this time well demonstrates the strong implementation capability of its technical team.
According to Li Zonglin's introduction at the launch event, XHEART went through approximately two key developmental stages from establishment to chip tape-out, and then to mass production. Within eight months after mass production, the cumulative shipments of the X7 series exceeded 200,000 units, deployed in 10 mass-produced vehicle models, and secured orders for over 40 vehicle models.
He also reviewed the early verification process of the X7 series: less than 24 hours after the X7 chip returned, it lit up, with main data paths connected; after continuous磨合 by hardware, software, and algorithm teams, a closed loop on the vehicle was achieved in 17 days, and testing began on real roads.
Li Zonglin particularly emphasized that these advances were not solely due to quick debugging after chip return, but stemmed from the completion of extensive verification work in advance.
Before tape-out, XHEART conducted full-chip simulation verification using mass-production large model algorithms with Momenta, a leading player in the domestic intelligent driving algorithm field, and repeatedly verified against data from different scenarios. On the customer side, the company also participated early in domain controller design, integrating and verifying the chip with other components selected by the customer, rather than dealing with hardware-software synergy issues only after the chip returned.
"We only have one chance, so we are cautious, transparent, and pragmatic," Li Zonglin explained to Xinzhixun. Startup chip companies must minimize risks such as tape-out failure, unsuccessful hardware-software integration, and delays in customer projects, because the closer to mass production, the more manpower and capital required.
This engineering mindset is also reflected in XHEART's choice of customer delivery mode. Although XHEART is not a Tier 1 supplier directly providing hardware systems to automakers, it provides reference designs around the X7 series chips and verifies them according to OEM mass production standards, including extensive DV/PV testing at the domain controller level. This also helps accelerate the deployment of the X7 series in vehicles.
For automakers, chip performance is only part of the selection criteria. Whether the chip can integrate smoothly with existing software, sensors, domain controllers, and vehicle systems, whether it meets reliability and safety requirements, and whether suppliers can promptly resolve issues during project development also determine whether the product can be mass-produced on schedule.
Li Zonglin proudly stated that an important reason automakers choose X7 series chips is that after adapting to end-to-end large models, the chips deliver satisfactory Urban NOA and L2++ experiences, facilitating the adaptation of solutions to more vehicle models.
Therefore, XHEART's competitive barrier cannot be simply understood as an NPU architecture innovation. More accurately, it requires simultaneously establishing three capabilities: chip design capability oriented towards large models, engineering capability for hardware-software and vehicle system integration, and the ability to continuously deliver in multi-model mass production. Among these, technical architecture can be established through R&D, but mass production experience, customer verification, and system integration capabilities often need to be accumulated gradually through real projects. This is the value behind XHEART's rapid commercialization progress.
V. Momenta is a "Co-Creator," Not a "Binding Partner"
In XHEART's product roadmap, Momenta is an unavoidable important strategic partner.
At the launch event, Momenta CEO Cao Xudong pointed out that the value of world models lies in enhancing the ability to understand, deduce, and predict the physical world. He also announced that the upcoming R7 Ultra world model will run on the XHEART X7 Ultra, with model parameters scaling up 5-10 times from the original, and safety performance improving 5-10 times. It is estimated that the next-generation world model parameters may see a 10-100 fold increase.
He viewed intelligent driving as an important pioneering application of Physical AI, believing that 2028 will be the detonation point for L4 intelligent driving, and expressed willingness to join hands with XHEART to lead the development opportunities of the2028 L4 explosion.
For XHEART, Momenta is not just an algorithm partner but also provides important input for defining chip architecture.
Data published by Momenta shows that its cumulative mass-production deployment has exceeded 1.4 million units, with cumulative driving mileage reaching 20 billion kilometers. The latest addition of 100,000 mass-production deployments took less than one month. This accumulation of data from real vehicles provides a foundation for models to encounter more scenarios and learn more driving experience.
Since chip R&D cycles are long while large model algorithm iterations are fast, if both parties can discuss future model trends together during the initial chip design phase, they have the opportunity to identify needs in computing power, bandwidth, operators, and toolchains in advance.
Regarding whether XHEART is bound to Momenta, Li Zonglin told Xinzhixun that the cooperation is non-exclusive. Other algorithm suppliers based on Transformer architecture algorithms can also adapt and develop based on XHEART chips.
He explained that through early joint definition and verification, both parties grasp the development trends of model technology, while core work such as chip architecture and design is independently completed by the XHEART team. Commercially, XHEART sells SoC chips independently without bundling Momenta algorithms, allowing OEMs to freely choose chip and algorithm solutions.
VI. Intensifying Competition in Intelligent Driving Chips: What Makes XHEART Stand Out?
XHEART hopes to start with intelligent driving and empower multi-domain AI experiences relying on large model chips. Currently, there are many competitors in the intelligent driving chip market, including third-party suppliers like NVIDIA, Qualcomm, Horizon Robotics, and Black Sesame Technologies, as well as automakers like Tesla, BYD, Li Auto, NIO, and Xiaomi continuing to push self-developed chips. Different vendors possess their own technical architectures, customer resources, and ecosystem advantages. New entrants seeking market share clearly cannot stand out by relying solely on one or several performance metrics.
Li Zonglin emphasized that XHEART focuses more on its own goals, team, and execution. He believes that numerous competitors indicate industry participants' optimism about the market. But what truly matters is whether a company can consistently deliver valuable solutions to customers.
Looking at the product design and mass production path of the X7 Ultra, XHEART's differentiation is mainly reflected in the following aspects.
First, differentiation in the product definition stage. XHEART does not simply pursue generic computing power stacking but chooses targeted optimization around end-to-end large models like Transformers, hoping that its 700 TOPS computing power achieves higher computational utilization and lower data movement overhead under real model loads.
Second, differentiation in hardware-software synergy. XHEART attempts to combine algorithm needs, chip architecture, toolchains, domain controller reference designs, and mass production verification to reduce engineering costs and time from chip R&D to vehicle deployment.
Third, differentiation in business strategy. Through deep cooperation with Momenta, XHEART gains input on advanced model needs; by adhering to non-exclusive cooperation and independent sales, it retains space for expanding to other model algorithm partners and more OEM customers in the future.
However, differentiation in technology and business strategy does not automatically equate to a competitive barrier. Whether "defining chips by large models" holds long-term advantage ultimately still needs to withstand inspection in several areas:
First, whether the chip can continue to maintain high utilization and energy efficiency advantages after models continue to evolve; second, whether products can expand from existing vehicle models to more customers and price ranges; third, whether R&D investment, chip costs, and company operating costs can be kept within reasonable limits; fourth, whether the existing architecture can continue to evolve when higher levels of autonomous driving impose stricter requirements on system safety, reliability, and determinism.
These issues collectively determine whether XHEART can grow from a successfully mass-produced chip into a platform-type chip enterprise with continuous product iteration and large-scale delivery capabilities.
VII. Capital and Supply Chain: Industrial Synergy Behind CXMT and TSMC
The chip industry exhibits typical economies of scale. Massive R&D investments occur upfront, while product mass production and revenue returns take longer to materialize, and chip yield and shipment volumes must reach sufficient scales to potentially generate profits. Therefore, for a startup chip design enterprise, while the correctness of the chip technology route is crucial, obtaining capital and industrial chain support, and effectively controlling R&D and operating costs, are equally vital for the company's sustainable development.
Li Zonglin pointed out that XHEART has placed special emphasis on financial health since its inception, hoping to effectively control chip costs and operating costs. Based on current assessments, the X7 series chips are already able to support the company's healthy financial operations. He also emphasized that chip companies cannot stay at the PPT demonstration stage but must truly deliver products to customers, form business returns through customer recognition, and reinvest earnings into continuous R&D.
"We deliver value to customers, customers bring business returns, and these returns support the team's continuous iterative R&D." In Li Zonglin's view, forming such a positive cycle depends on the synergy between technology routes, cost control, and execution discipline.
Support from capital and industrial resources provides another layer of foundation for realizing XHEART's positive cycle.
In early October, XHEART announced the completion of a new round of strategic financing. European top automaker Renault Group invested for the first time, Chery Automobile added investment, along with numerous institutions including domestic memory giant CXMT, SAIC Motor, IDG, and NIO Capital.
CXMT's investment in XHEART attracted particular external attention as a key supplier in the memory field. XHEART primarily develops SoC chips, while CXMT manufactures memory chips. The correlation between SoCs and DDR memory in terms of system performance and cost is strengthening. No matter how high the theoretical computing power of a chip, it may still be limited by the "memory wall" if memory bandwidth is insufficient or data movement efficiency is low.
Therefore, synergy between SoC design and the memory supply chain helps consider performance, cost, and reliability from a system perspective. Future cooperation between the two parties around common customers, product verification, and solution delivery is expected to deepen.
Another important supply chain partner for XHEART is TSMC (Taiwan Semiconductor Manufacturing Company). At this launch event, Dr. Chen Ping, Vice President of TSMC, appeared as a special guest to introduce the cooperation with XHEART.
Dr. Chen Ping recalled that three years ago, when Li Zonglin and his team proposed designing chips based on large models and hoped to gradually push L3 and L4 autonomous driving capabilities into real-world applications, this vision seemed quite challenging. But as the X7 series moved toward mass production, TSMC provided process support and services for the X7 series chips.
Chen Ping summarized the current development of AI chips in semiconductor manufacturing into two important technical main lines: first, the continuous shrinking of logic processes; second, expanding system performance through advanced packaging and chip integration. However, there are differences in reliability requirements between vehicle-grade chips and consumer chips; vehicle-grade processes need to accumulate more mass production data and undergo thorough verification. Facing L3, L4 autonomous driving and higher computing power demands, advanced processes and advanced packaging may play increasingly important roles.
Chen Ping also stated that TSMC is prepared in terms of advanced processes and hopes to continue cooperating with XHEART in the future, leveraging vehicle-grade 5nm, 3nm, and other advanced processes to drive the development of higher-performance chips.
Clearly, from the perspective of capital and industrial chains, XHEART's current achievements do not rely solely on its own chip design team. Capital support, advanced manufacturing, memory supply, algorithm models, domain controller design, and full-vehicle verification are all key factors enabling its products to move toward mass commercial use.
This also reveals a key characteristic of competition in vehicle-grade intelligent driving chips: the competitiveness of chip design companies comes not only from core technologies they master but also from whether they can obtain sufficient funding support and coordinate industrial chain resources to strike a balance among performance, power consumption, cost, reliability, and delivery cycles.
VIII. From X7 to X9: L4 Is Not Simple Addition of Computing Power
Alongside the official release of the X7 Ultra, XHEART also announced the R&D targets for its next-generation chip aimed at L4 needs—the X9.
According to information disclosed by XHEART, the X9's target large model computing power is 3,000 TOPS, with a single-chip memory bandwidth target of 700 GB/s, catering to larger-scale models, as well as edge-side Physical AI scenarios such as L4 autonomous driving and embodied intelligence.
Li Zonglin stated that XHEART's R&D rhythm is "mass-produce one generation, develop one generation, preview one generation." The X7 Ultra represents the current stage's hardware-software synergy achievements, while the X9 will continue to unfold design around the computational and storage needs of larger-scale models.
It should be noted that moving from L2 to L4 in intelligent driving is not simply a matter of adding computing power. Li Zonglin pointed out in an interview that going from L2 to L4 is an upgrade in the computing paradigm. Besides boosting TOPS, chips must also consider bandwidth, on-chip storage capacity, deterministic latency, and higher safety fallback capabilities.
Therefore, what is finally delivered to automakers is not an isolated computing core, but an automotive computing platform that needs to simultaneously handle model inference (NPU), system control (CPU), sensor inputs, and safety requirements. On the X7 Ultra, XHEART has already embodied this thinking in sensor processing and safety design.
According to Li Zonglin, the X7 Ultra adopts a dedicated LiDAR processing accelerator, supporting a processing bandwidth of 20 million points per second to cope with the point cloud data processing needs brought by high-line-count LiDARs. Meanwhile, the X7 Ultra optimizes the camera processing pipeline, focusing not just on average latency but reinforcing latency determinism. Because a system with an average 30ms latency but a jitter range of 20 to 50ms has its safety floor determined by the 50ms mark. Through local computation and pipeline control, the X7 Ultra improves camera processing stability by 100% compared to competitors.
In terms of hardware safety, the X7 Ultra meets ISO 26262 ASIL-B functional safety requirements, with an embedded MCU reaching ASIL-D level, and information security meeting National Cryptography Level 2 requirements; in terms of driving safety, the X7 Ultra possesses efficient computing power benchmarking industry flagships and reserves potential for continuous model upgrades.
Meanwhile, XHEART disclosed that the X7 series has been introduced into multiple L3 and L4 autonomous driving projects, and a reference computing platform based on two X7 chips has been launched. This solution features redundant power supplies, sensor access, and communication interconnection designs, targeting the system requirements of higher-level autonomous driving.
This indicates that besides existing L2++ mass production business, XHEART's intelligent driving chips have already accumulated chip and system capabilities required for higher-level autonomous driving in advance.
Regarding the broader embodied intelligence market, Li Zonglin stated in an interview that the technical foundations of autonomous driving and embodied intelligence share high similarity. The company will develop towards robots and humanoid robots in the future and has already engaged in project exchanges with some robot enterprises.
However, different scenarios still have varying requirements for sensors, real-time control, power consumption, and reliability; automotive chips cannot be directly used in robots without adjustment. Whether XHEART can transform its accumulated experience in architecture design and hardware-software synergy in the automotive sector into competitiveness in the robotics field still requires verification through subsequent products and projects.
Summary:
From choosing "defining chips by large models" at its inception in 2023, to the mass production of X7 series chips achieving over 200,000 shipments, to the release of the X7 Ultra and the exposure of the next-generation X9, XHEART is establishing a development path starting with large model needs, centered on hardware-software synergy, and grounded in mass production delivery.
The value of this route lies not only in providing a more suitable computing architecture for end-to-end large models but also in incorporating chip design, algorithm evolution, toolchain optimization, system verification, and supply chain synergy into the same product development logic. However, from proving the route works to achieving long-term commercial success, numerous challenges remain.
For XHEART, the key in the next stage is not just launching the X9 with higher computing power, but maintaining product performance and energy efficiency advantages while expanding shipment volumes; truly expanding an open ecosystem while deepening cooperation with Momenta; continuously accumulating system safety and mass production delivery capabilities while advancing L3 and L4 projects; and ultimately, through economies of scale, turning continuous R&D into a financially sustainable profitable positive cycle. This will determine whether it can truly gain a foothold in the fierce competition of the chip market.
Author: Xinzhixun - Langke Jian