Author: Jiu Lin
Wafer-scale chips are stepping into the spotlight.
This year, OpenAI signed a three-year compute procurement agreement with Cerebras. The agreement involves up to 750MW of compute capacity, to be delivered in batches before 2028. External estimates suggest the potential total value of this agreement exceeds $20 billion.
Cerebras's product is precisely a wafer-scale chip, manufactured using a monolithic wafer-scale approach that relies entirely on lithography capabilities to fabricate an entire wafer into a single chip. Meanwhile, Cerebras also went public on the U.S. stock market this year. Financial data released in the first quarter after the IPO showed: revenue reached $193 million, a 94% year-on-year increase, and cloud service revenue surged 178% year-on-year.
Cerebras's orders have transformed wafer-scale chips from a manufacturing technology issue into a computing industry issue. At the same time, Cerebras is not the only one betting on the wafer scale. Tesla has restarted Dojo 3; in China, universities, research institutions, and enterprises have successively announced 12-inch verification prototypes, multi-chiplet prototypes, and product roadmaps. Wafer-scale chips are becoming a realistic choice for the AI compute industry.
01. Why Does AI Need to Move to the Wafer Scale?
The bottleneck of AI systems is shifting from computation to data movement. During model execution, weights and activations need to be repeatedly transferred between compute and memory, and multiple chips must continuously exchange and synchronize data. Once data leaves the chip, it must pass through package I/O, PCBs (Printed Circuit Boards), network interface cards, switch chips, and optical modules. The larger the cluster, the higher the power consumption and cost spent on communication, and the harder it is for newly added GPUs to translate into proportional effective compute.
The industry currently has two solution approaches. One is to continue expanding the rack-scale compute domain. For example, NVIDIA's GB200 NVL72 organizes 72 GPUs into a liquid-cooled rack via NVLink; Huawei's CloudMatrix 384 forms a supernode with 384 Ascend 910C chips and high-speed interconnects. That is, in the form of supernodes, many independent chips are connected through more powerful switch chips, copper cables or optical connections, and system software, making the rack behave more like a single computer.
The other approach is to shorten physical distances. Wafer-scale systems compress data exchanges that originally occurred between boards and racks into the package or even the wafer itself, replacing centimeter- and meter-scale networks with millimeter-scale interconnects. Its core value lies not in adding more compute units, but in reducing data movement.
Both routes involve trade-offs. The supernode approach has a mature software ecosystem, making it easier to scale and replace hardware, but it incurs higher networking costs; wafer-scale systems trade highly customized manufacturing, power delivery, cooling, and software for higher bandwidth, lower latency, and higher energy efficiency.
In July this year, AMD and Cerebras announced a disaggregated inference collaboration, where AMD Helios handles the compute-intensive prefill and Cerebras WSE handles the latency-sensitive decode. The two companies calculated that this combination can improve Tokens/Watt by up to 5x compared to using WSE alone. This indicates that wafer-scale chips are not necessarily meant to replace GPUs, but are more likely to become a layer in heterogeneous data centers, taking over communication-intensive and latency-sensitive workloads.
02. Wafer-Scale Chips: Two Distinct Paths
Traditional large chips are first constrained by lithography dimensions. The area covered by a single exposure in advanced lithography is about 800+ square millimeters, which is commonly known as the reticle limit. Taking NVIDIA's H100 as an example, its die area is approximately 814 square millimeters, already approaching this limit.
Continuously increasing transistor counts used to rely primarily on process node scaling; however, as the R&D, design, and manufacturing costs of advanced process nodes continue to rise, the industry has begun to use chiplets to partition complex chips and reassemble them via advanced packaging. Wafer-scale computing, on the other hand, expands the system boundary from a single package to nearly an entire wafer. Strictly speaking, what the industry usually refers to as "wafer-scale chips" actually encompasses two types of wafer-scale computing systems.
The first type is a monolithic single-logic system across the entire wafer. Cerebras's Wafer Scale Engine (WSE) is currently the most typical and the only product that has achieved true commercial delivery. After the wafer is manufactured, it is no longer diced into individual dies; instead, the entire wafer is organized into a continuous logic system through cross-reticle interconnects.
Cerebras's choice is: one entire wafer is one chip, solving yield first, then controlling the entire system. The WSE-3 is built on the 5nm process, with an area of 46,225 square millimeters, integrating 4 trillion transistors and 900,000 AI cores, delivering a peak performance of 125 PFLOPS. For comparison, the die area of advanced GPUs is still constrained by the single-exposure lithography area, making the WSE-3's area equivalent to dozens of reticle fields.
This high level of integration also requires Cerebras to control more segments of the industry chain. The WSE cannot be plugged into a standard server like a PCIe accelerator card; the company needs to simultaneously design wafer-scale packaging, power delivery, liquid cooling, the complete machine, compilers, and cluster software. What Cerebras actually sells is not a standard chip, but a computing system that extends from the silicon wafer to cloud services.
The second type is a reconfigurable multi-chiplet wafer-scale system. This approach first manufactures, dices, and tests chiplets, and then re-integrates the known good dies onto a wafer-scale interconnect platform. Tesla Dojo is the most representative industry case: Tesla is responsible for the D1 chip, training architecture, and software, while TSMC (Taiwan Semiconductor Manufacturing Company) uses InFO_SoW wafer-level fan-out packaging to assemble 25 D1 chips into a Training Tile.
Compared to Cerebras, this route does not require a flawed entire logic wafer to keep functioning. Chips can be individually tested after manufacturing, and only known good dies are selected for integration, thereby reducing the yield risk in front-end manufacturing. It also makes it easier to mix chiplets with different process nodes and functions.
Following Dojo, TSMC began expanding wafer-scale integration from a single-customer project into a general-purpose foundry platform. According to TSMC's published roadmap, the SoW-X plan aims to further integrate logic chiplets, HBM, and I/O, targeting production in 2027. SoW-X is not the next-generation product of Dojo, but rather TSMC's next-generation wafer-scale platform offered to a broader range of HPC and ASIC customers.
In addition, there is a group of technologies easily confused with wafer-scale computing, including wafer-level packaging, hybrid bonding, and 3D stacking. These processes complete redistribution, packaging, or vertical connections at the wafer stage, but the final product may still be a standard-sized package. They are crucial technological foundations for wafer-scale computing, but they do not equate to wafer-scale computing systems.
03. New Progress in China's Wafer-Scale Chips
Over the past two years, domestic wafer-scale computing has seen considerable progress. Although no commercial systems with the same maturity level as Cerebras have emerged yet, it has moved far beyond mere conceptual research.
In the academic sector, in 2025, the team of Yin Shouyi and Hu Yang from Tsinghua University had three wafer-scale computing results accepted at ISCA simultaneously. The research objects are full-wafer compute topology, integrated architecture, and large model inference mapping, respectively. These three works correspond to the three levels of a wafer-scale computer: how to connect chiplets at the bottom layer, how to organize compute and memory in the middle layer, and how to map large models to hardware at the top layer.
In paper experiments, their topology scheme achieved a 2.39x throughput improvement compared to Dojo; the integrated architecture achieved 2.90x compute power, 2.11x communication bandwidth, and 11.23x memory bandwidth under the same cost model; the WSC-LLM mapping scheme achieved an average performance improvement of 3.12x compared to the GPU clusters selected in the paper. Meanwhile, the team, in collaboration with Tsingmicro, successfully developed a 12-inch wafer-scale AI chip verification prototype, realizing "One Wafer One Chip."
Another noteworthy achievement is "Yingtianhu," developed by institutions including the Institute of Computing Technology, Chinese Academy of Sciences. "Yingtianhu" was jointly completed by the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences (CAS), the 58th Research Institute of China Electronics Technology Group Corporation (CETC), and the Wuxi Xinguang Interconnect Technology Research Institute. It adopts a decoupled architecture of "compute module—interconnect substrate," attempting to accommodate various chiplets such as CPU, AI, DSP, switching, and memory on the same platform.
The paper disclosed that the team completed a prototype system consisting of 16 compute modules. The relevant chips were taped out using TSMC's 28nm process, achieving petaflop-level computing capability per single wafer. In the experiments set in the paper, the relevant metrics for high-performance linear algebra and deep learning inference tasks improved by approximately 1.45x and 1.78x, respectively.
This year, a research team from the Institute of Computing Technology, CAS, proposed Ouroboros. This is a processing-in-memory (PIM) architecture based on wafer-scale SRAM, adopting a massive wafer-scale integration scheme. On a 12-inch wafer, the research team integrated 54GB of SRAM. This capacity is sufficient to fully keep the parameters, activations, and KV Cache of mainstream 7B, 13B, and even larger-scale models resident in the first-level memory. It can achieve an average throughput 4.1 times that of existing top-tier systems, with average energy efficiency improved by 4.2 times. Its performance is particularly outstanding on 13B parameter-scale models: throughput reaches up to 9.1 times higher, and energy efficiency improves by up to 17 times. When using a single wafer to infer the Llama 13B model and testing on the WikiText-2 dataset, the system throughput can stably reach 150,000 tokens/s.
On the enterprise side, signals of productization are also beginning to emerge. In May this year, New Unigroup released the "Zixian" 3D near-memory computing architecture, which adopts 3D DRAM and a pioneering 3.5D heterogeneous and diverse integration route. Through advanced packaging, memory units and compute units are stacked in 3D, significantly shortening the data transmission distance. According to the data, memory bandwidth can reach 30TB/s, surpassing the industry's latest HBM4 standard; under the PNM near-memory computing mode, memory access latency is reduced by up to 18 times; simulation results show that under the same compute conditions, the Token throughput rate is 1.5 to over 2 times higher than international flagship products. Chen Jie, Co-President of New Unigroup, stated: "The 'Zixian' architecture integrates 10 to 20 different types of dies into a single chip, which has approached the physical limits of single-chip scaling. The next step of deeper integration must rely on wafer-scale technology to be realized."
It is understood that Tsingmicro's reconfigurable computing has evolved from 1.0 and 2.0 to the 3.0 released this time, and the next step will enter 4.0 targeting wafer-scale computing; its products have evolved from the TX81, which supports dataflow and grid computing, to the TX82, which supports 3D computing, and further to the planned wafer-scale chips.
In the interconnect segment, Jingxin Microelectronics has launched software-defined interconnect chips and bridging products. Its SDI3210 supports up to 32 ports or 32 high-speed channels, and the PRB0400 PCIe Gen2/RapidIO Gen2 bridging chip has already been mass-produced. In 2026, the company also released RDMA peer-to-peer communication IP and dedicated middleware for wafer-scale systems.
04. Conclusion
Currently, wafer-scale computing has moved from technical validation to industrial validation. The next competition will no longer be about area and transistor count, but about performance, power consumption, cost, and delivery capabilities under real-world workloads.
It will not replace GPUs and supernodes, but it may be the first to enter communication-intensive AI inference and specialized computing. For China, the opportunity is not to replicate a WSE, but to combine chiplets, interconnects, packaging, and software into usable wafer-scale systems.
Wafer-scale chips will become the next key battleground.