Compiled by | Cui Yuanwei Edited by | Chen Junda
Xindongxi reported on October 9 that yesterday, GlobalFoundries, a major global semiconductor foundry, announced a multi-year manufacturing agreement with TSMC to establish a silicon interposer production base in the U.S., supplying TSMC's CoWoS advanced packaging ecosystem. The agreement is valued at approximately USD 2 billion (equivalent to about CNY 13.4 billion). GlobalFoundries will expand the capacity of its Malta, New York facility to provide manufacturing services for TSMC, becoming the first U.S. supplier of silicon interposers for advanced packaging technologies. The project's scope includes components such as embedded deep trench capacitors. Mass production ramp-up is expected to begin in the first half of 2028. The initial term of the agreement is five years, with a framework reserved for future capacity expansion based on customer demand.
CoWoS is TSMC's 2.5D advanced packaging technology. Its core approach is to insert an interposer between the chip and the packaging substrate, achieving high-density interconnects through Through-Silicon Vias (TSV), enabling logic chips and High Bandwidth Memory (HBM) to work collaboratively within a single package. It addresses the "data movement" bottleneck in AI chips: no matter how strong the computing power of a single chip is, it will be dragged down if the memory bandwidth cannot keep up. CoWoS enables the tight integration of multiple chips and HBM, shortening interconnect distances, increasing bandwidth, and reducing power consumption. It is the key enabler behind AI accelerators from manufacturers such as NVIDIA and AMD. CoWoS has three technical routes: CoWoS-S is the mainstream solution for current AI GPUs. It uses a single monolithic silicon interposer, connecting the upper-level chips and the substrate via TSVs, offering the highest performance ceiling. The silicon interposer carries the circuitry required for transmitting electronic signals and power, allowing multiple chips within the package to work together. However, the larger the interposer area, the more difficult it is to control the yield and the higher the cost.
CoWoS-R utilizes a multi-layer Redistribution Layer (RDL) interposer, wired with polymers and copper traces, resulting in lower costs. CoWoS-L combines the advantages of both, using RDL for large-area routing while embedding small blocks of Local Silicon Interconnect (LSI) in areas with high bandwidth demands, balancing performance and package size. The silicon interposers supplied by GlobalFoundries this time are primarily intended for the CoWoS-S route.
As AI chip sizes grow and multiple chips are integrated into a single package, the tight capacity of CoWoS has become a core bottleneck restricting AI chip deliveries. TSMC is responding with a roadmap of capacity expansion and technology iteration: in terms of capacity, the monthly CoWoS capacity is ramping up from approximately 35,000 wafers at the end of 2024 to a target of 130,000 to 140,000 wafers by the end of 2026, and is expected to double to about 260,000 wafers by the end of 2028. In terms of technology, TSMC's package sizes are expanding year by year: the 5.5x reticle size interposer has been mass-produced in 2026. In 2028, it will introduce a 14x reticle size version integrating 20 HBM stacks, and in 2029, it will further expand to 24 HBM stacks.
Founded in 2009 and headquartered in Malta, New York, GlobalFoundries was established as a joint venture between the UAE sovereign fund Mubadala and AMD. It is a globally leading semiconductor foundry with manufacturing facilities across the U.S., Europe, and Asia, including plants in Malta, New York, and Burlington, Vermont in the U.S., Dresden in Germany, and Singapore. The company focuses on differentiated processes and specialty technologies, providing chip products for AI deployment scenarios from the cloud to the edge in fields such as RF and Gallium Nitride (GaN) power devices. In the realm of advanced packaging, GlobalFoundries' 65PKG silicon interposer platform achieved mass production qualification in 2024, reaching Technology Readiness Level (TRL) 9. It incorporates TSV technology, supporting wafer-to-wafer and chip-to-wafer integration, enabling the interconnection of heterogeneous logic, memory, and power devices in a 3D architecture.
In May 2026, the company launched the SCALE co-packaged optics solution based on silicon photonics technology for AI data centers, having demonstrated 8λ and 16λ bidirectional dense wavelength division multiplexing transmission. In June, it announced that the SLATE wafer-to-wafer bonding technology is ready for mass production on the 9SW RF platform. Ed Kaste, Senior Vice President of CMOS Business at GlobalFoundries, stated that advanced packaging is increasingly critical to the performance, energy efficiency, and scale of next-generation AI systems. GlobalFoundries will leverage its U.S. manufacturing footprint to provide a secure and scalable supply source for this critical segment.
Conclusion: New U.S. Supply Point Added to Advanced Packaging Supply Chain Seeking Relief for AI Capacity Bottlenecks
The competition for AI chip capacity is extending from front-end processes to the packaging segment. TSMC's CoWoS packaging previously relied heavily on Asian capacity. Following the implementation of this collaboration, a new domestic U.S. supply source has been added to this critical link, also reflecting the trend of AI supply chain localization expanding from wafer manufacturing to packaging components.
For GlobalFoundries, this order extends its business into the field of advanced packaging materials, expanding its participation in the AI industry chain. However, GlobalFoundries' mass production will not begin until 2028. Whether it can truly alleviate the tight capacity of advanced packaging at that time will depend on the ramp-up speed of the new capacity and the evolution of overall supply chain bottlenecks. Source: GlobalFoundries