Author: Junxi
On September 10, TSMC (Taiwan Semiconductor Manufacturing Company) announced its August revenue of TWD 514.805 billion, up 10.1% month-on-month and 53.32% year-on-year. This marks the first time the company's monthly revenue has exceeded TWD 500 billion, and it is the fourth consecutive month of setting a new record. According to disclosures from the second-quarter earnings call, nodes at 7nm and below collectively accounted for 77% of wafer revenue.
Actions on both the capacity and technology fronts have emerged intensively in the same period. According to media reports, the monthly wafer start volume for 3nm approached 150,000 wafers in the first half of the year, and the year-end target of 180,000 wafers may be achieved as early as the beginning of the fourth quarter; five 2nm fabs are ramping up simultaneously; and nearly 20 TSMC fabs are under construction globally. On September 1, the company stated at SEMICON Taiwan that microfluidic channel cooling has been incorporated into its R&D roadmap; on September 8, it jointly announced with ASML the push to double the reticle size; and earlier, a paper on single-layer molybdenum disulfide transistors, co-authored with National Yang Ming Chiao Tung University and Academia Sinica, was published in Nature Electronics.
These initiatives span process, packaging, lithography, and materials, yet they all point to the same shift. Over the past two decades, each advancement to a new process node drove down the cost per transistor, allowing chip design companies to pass on a portion of the performance gains to end-product prices. However, at the 3nm and 2nm nodes, advanced capacity has been in chronic short supply, and overseas fab construction has driven up depreciation, flattening this curve. When shrinking transistors no longer automatically yields cheaper computing power, improvements must be sought elsewhere: larger exposure areas, larger packages, higher power density, and channel materials beyond silicon.
01, 3nm Ramps Up Ahead of Schedule with Synchronous Price Hikes
The acceleration of 3nm is driven by additional orders from major clients. According to TrendForce, the year-end target of 180,000 wafers is expected to be achieved two to three months ahead of schedule, with demand coming from NVIDIA, AMD, and Broadcom. Broken down by process node, 5nm contributed 33% and 3nm contributed 30% in the second quarter, while the newly commercialized 2nm contributed 3%. To free up capacity, TSMC has converted some 5nm equipment to 3nm production lines, and has also planned new 3nm fabs in Taiwan, China, Arizona, and Japan.
The monthly capacity for 2nm was 50,000 to 60,000 wafers in the first half of the year, is expected to exceed 80,000 wafers at the beginning of the fourth quarter, and will approach 100,000 wafers by year-end. TSMC Senior Vice President Y.C. Hou previously mentioned that in 2026, five 2nm fabs will ramp up simultaneously (two in Hsinchu and three in Kaohsiung), with the first-year wafer output target 45% higher than the first-year output of 3nm in 2023. Combined, the two nodes will see a monthly wafer start volume exceeding 260,000 wafers at the beginning of the fourth quarter.
Prices have been raised accordingly. According to reports, TSMC's 3nm prices could see a maximum increase of up to 15% in the second half of 2026, with an additional 5% to 10% room for adjustment in 2027; other reports indicate that this round of price hikes covers approximately 75% of wafer revenue, encompassing all nodes at 7nm and above.
Depreciation pressures exist simultaneously. TSMC's consolidated revenue in the second quarter was TWD 1.27 trillion, a year-on-year increase of approximately 36%, with a gross margin of 67.7%. However, the company noted that the rapid ramp-up of 2nm will drag down the gross margin by 3 to 4 percentage points in the second half of the year, and the dilution effect from overseas fabs will expand to 3% to 4% in the coming years. For clients like NVIDIA and AMD, moving forward to the next node means that every bit of performance gain becomes more expensive.
02, Twenty Fabs Under Construction Simultaneously, the Bottleneck is Not Capital
The July earnings call raised the 2026 capital expenditure from the beginning of the year estimate of USD 52 billion to USD 56 billion, up to USD 60 billion to USD 64 billion, while also announcing an additional USD 100 billion investment in the United States, bringing the cumulative investment plan for Arizona to USD 265 billion. According to public reports, TSMC currently has nearly 20 fabs under construction globally, including 13 in Taiwan, China, and 5 to 6 overseas. For reference, the company historically typically advanced 4 to 5 fab construction projects simultaneously.
The changes in equipment procurement are even steeper. From the end of 2025 to July 2026, TSMC's estimated demand for fab equipment first rose to 1.5 times the original plan, and then to 1.9 times, nearly doubling within half a year. Y.C. Hou stated that in the past 30 years, he has never seen demand change so drastically and so frequently; the company cannot meet all the needs of all customers and can only try its best to catch up.
What is in short supply is skilled fab construction manpower, not capital. Industry insiders point out that after the main structure is topped out, the installation of cleanrooms, special gas pipelines, electromechanical piping, and equipment move-in face the same problems in Taiwan, China, and Arizona. The training cycle for these types of jobs is measured in years, and it cannot be made up in a single quarter by adding capital expenditure. Over the past two decades, discussions on advanced processes have almost entirely revolved around lithography machines, yield rates, and R&D investment, with fab construction tacitly assumed to be a phase that could be completed on schedule; when the number of simultaneously started projects has increased four to five times, this assumption no longer holds true.
The schedule is still advancing ahead of time. The second Arizona fab will begin equipment installation in the third quarter of 2026, targeting mass production of 3nm in 2027, ahead of the originally scheduled 2028; the new 1.4nm fab in Phase 2 of the Central Taiwan Science Park in Taiwan, China, will begin trial production as early as the third quarter of 2027. However, these are construction and equipment installation schedules, which do not mean that capacity has already been formed; the actual output of this batch of fabs will be concentrated between 2027 and 2029.
03, Post-Moore's Law, the Source of Performance Growth Shifts
On September 8, TSMC and ASML jointly announced that they will jointly push the industry to transition reticles from 6 inches to 12 inches. TSMC plans to introduce ASML's High NA EUV (Extreme Ultraviolet) lithography machines starting in 2030, with a 12-inch reticle pilot line expected to be built in 2031 and introduced into advanced process mass production in 2033; meanwhile, Samsung and Intel also support this standard.
A reticle is a template used to project circuit patterns onto a wafer, and its size determines how large a chip area can be drawn in a single exposure. To improve resolution, High NA EUV adopts an optical structure that magnifies eight times in one direction, at the cost of a single exposure area being only half that of existing EUV machines. If a chip exceeds this area, it requires two exposures and subsequent stitching, which discounts both yield and capacity; doubling the reticle size essentially gives back this area. Some analyses have listed reticle pod manufacturers such as Gudeng Precision as beneficiaries, but the mass production timeline is in 2033. In between, it must undergo pilot line verification and supply chain adaptation. Currently, this is a roadmap, not capacity that can be counted in.
Another way out for area lies in packaging. According to Chen Yen-ming, Director of Advanced Packaging R&D at TSMC, the packaging area of CoWoS is expanding from 3.3 times the reticle size in 2024 to over 14 times by 2029. By then, a single package can integrate 24 HBM (High Bandwidth Memory) chips, with the transistor count increasing 48 times compared to 2024, and memory bandwidth growing 34 times. A single chip cannot be made larger due to reticle limitations, but stacking multiple chips into the same package currently has no such upper limit.
After packaging is scaled up, heat becomes the new constraint. Chen Yen-ming stated that thermal management "is not going to be a bottleneck, but is already a bottleneck": AI computing power is currently growing four to five times annually, and the total power consumption of a single package will increase by about six times in the near future. The enlargement of package size will also simultaneously tighten the warpage and reliability windows. The single-chip power consumption of NVIDIA's next-generation Rubin Ultra has reached the 2,300-watt level, and the entire rack's power consumption is expected to be about 600 kilowatts, which is difficult to handle with traditional air cooling and cold plates.
TSMC's solution is to introduce coolant directly inside the chip. Traditional liquid cooling attaches a cold plate to the package surface, separated by a lid and thermal interface material, with water channel widths in the 1 to 3 millimeter range; microfluidic channels, on the other hand, etch micrometer-level channels directly into the back of the silicon or inside the lid, allowing the coolant to flow directly past the heat-generating areas. A liquid cooling paper published by the company at the Electronic Components and Technology Conference provides measured data: the power density on the back of the logic chip exceeds 7 watts per square millimeter, controlling the temperature difference within 63 degrees Celsius under a thermal design power of over 2.6 kilowatts, and the thermal resistance from the chip junction to the ambient is improved by about 15% compared to the lidded liquid cooling solution with thermal interface material. However, the company's phrasing is "incorporated into the R&D roadmap," without announcing the introduction node or customers, which is not the same concept as mass production.
The channels must be etched on the silicon wafer and hermetically packaged using fusion bonding; thus, thermal management shifts from a mechanical component to a semiconductor process, and the power to define the thermal budget also shifts from server manufacturers and thermal module manufacturers to the wafer foundry and packaging segments. According to reports, the heat dissipation capacity of microchannel lids can reach over 3,000 watts, with a unit price three to seven times that of cold plates. Jiance has passed NVIDIA's verification, and Asia Vital Components and Auras Technology are also deploying in this area. Processing precision, coolant leakage and corrosion, metal particle deposition, and maintenance difficulty have not yet been verified through large-scale mass production.
The third constraint lies in the materials themselves. The channel thickness of silicon has already approached the lower limit for normal operation, and making it any thinner will cause a significant drop in carrier mobility. The channels of 2D materials are only a few atomic layers thick, which theoretically better suppresses short-channel effects. The difficulty lies in the lack of dangling bonds on the surface, preventing the growth of gate dielectrics, and if forced growth occurs, it scatters electrons. In a paper published in Nature Electronics on July 31, the research team epitaxially grew aluminum on a single layer of molybdenum disulfide under ultra-high vacuum and oxidized it in situ to form a sub-nanometer aluminum oxide interface layer, then overlaid it with a hafnium oxide gate dielectric, achieving a device transconductance of 0.45 millisiemens per micrometer.
On June 15, imec (Interuniversity Microelectronics Centre), ASML, and TSMC jointly announced the first fabrication of 2D material transistors with a contact gate pitch of 50nm on a 300mm wafer, using molybdenum disulfide for the n-type channel and tungsten disulfide or tungsten diselenide for the p-type channel. 94% of the devices functioned normally, and Gouri Sankar Kar, Vice President of R&D at imec, stated that EUV (Extreme Ultraviolet) Lithography is the key to achieving this pitch. According to TrendForce's judgment, the commercialization of 2D materials remains a long-term goal and will not enter the mass production roadmap of any product generation in the short term; TSMC brought ASML and imec into the same path during the research stage so that when silicon reaches its limit, the option to change materials is held in its own hands.
04, Market Landscape and Validation Timelines
The competitive gap is still widening. According to statistics, in the first quarter of 2026, the revenue of the world's top ten wafer foundries was USD 47.95 billion, with TSMC accounting for 72% at approximately USD 35.86 billion, Samsung at 6.5%, and SMIC (Semiconductor Manufacturing International Corporation) at 5.1%. Behind the gap is the capital expenditure threshold: when a company can simultaneously start construction on 20 fabs and double equipment procurement within half a year, what the chasers need to make up for is not just the technological gap.
The tension in advanced packaging is easing, but not quickly. According to estimates, the supply-demand gap for CoWoS will converge from about 20% to around 10% by the end of 2026, with TSMC's monthly capacity in the range of 120,000 to 140,000 wafers, and it will expand by over 60% in 2027. These are estimates by research institutions, not realized capacity. Once capacity is no longer the only variable, whether 24 HBM chips and the resulting heat can be packed into a single package becomes a new competitive focus, and advanced packaging and thermal management thus shift from cost items to premium items.
The growth in the industry's total volume also needs to be broken down. The World Semiconductor Trade Statistics (WSTS) significantly raised its forecast on June 2, believing that the global semiconductor market size will reach USD 1.5112 trillion in 2026, breaking the USD 1 trillion mark for the first time, with a year-on-year increase of nearly 90%. Among them, memory chips are expected to grow by about 3.5 times to USD 803.9 billion, and logic chips will grow by 37.3% to USD 411.3 billion. The vast majority of the increase comes from the repricing of memory rather than proportional capacity expansion, and the growth rate of the logic foundry segment where TSMC operates is much more moderate than the total volume figures.
Divergence also exists. According to media statistics, the price-to-earnings ratio of the Philadelphia Semiconductor Index once reached about 71 times, the highest since the 2008 financial crisis, and the capital expenditure of the four major tech companies in 2026 will total approximately USD 725 billion. "The Big Short" Michael Burry likened the current state to the dot-com bubble era; other institutions believe that the supply constraints on high bandwidth memory are weakening industry cyclicality, and the price center may become more stable due to the shift towards long-term contracts. Neither judgment has been falsified by data yet.
05, Conclusion
The return window for this round of TSMC's investment is concentrated between 2027 and 2029, based on the premise that computing power demand will maintain high growth for at least another three to five years. The lesson from past cycles in the semiconductor industry is that there is a two- to three-year lag between capacity decisions and demand realization; the point of most resolute expansion is often also the point of lowest visibility. What needs to be tracked next is not whether the fabs can be built—as they are highly likely to be completed based on current progress—but whether the growth slope of AI computing power demand will still be there when this batch of capacity comes online.
A longer thread lies in the division of labor in the post-Moore era. Reticle enlargement will not happen until 2033, 2D materials have not entered the mass production roadmap, and microfluidic channels have not announced an introduction node; none of these three things constitute revenue at present, but they all point to the same judgment: after the cost per transistor stops declining, performance improvements are no longer determined by a single process node, but must be pushed forward simultaneously through lithography, packaging, thermal management, and materials. Only a few companies can mobilize these four fronts simultaneously, and system-level integration capabilities will replace process nodes as the pricing foundation for the next decade.