The large-scale deployment of Edge AI has long been constrained by a structural contradiction: while cloud-based large models possess immense capabilities, they suffer from high bandwidth costs, latency sensitivity, and prominent data privacy risks; conversely, edge devices generally lack sufficient computing power to handle real-time inference and multi-task concurrency. As the industry shifts from questioning "whether AI is feasible" to focusing on "how to make AI affordable and highly effective," defining the compute platform becomes critical.
At the 5th Dishui Lake China RISC-V Industry Forum, Du Yunhai, Senior Director of Marketing at Shanghai Tops Microelectronics, revealed that the EA6530, launched by the company last year, is an Edge AI SoC defined precisely against this backdrop. Instead of blindly chasing thousands of TOPS-level cloud computing power, it focuses on the real demands of industrial-grade edge scenarios—high compute density, high integration, and a low barrier to deployment.
Figure | Du Yunhai, Senior Director of Marketing at Shanghai Tops Microelectronics; Source: VeriSilicon
No Compromise on Compute Configuration, but with Clear Trade-offs
The EA6530 integrates an octa-core XuanTie C920v2 RISC-V CPU clocked at 2.0GHz, supporting the RVV 1.0 vector extension, with integer performance exceeding that of the Arm Cortex-A73 by over 20%.
Du Yunhai pointed out that on the edge, the CPU is not in a secondary role: pre- and post-processing of video streams, algorithm scheduling, SLAM and path planning, and multi-sensor synchronization all rely on the CPU's real-time response capabilities. From the very beginning of the design, Tops Microelectronics prioritized CPU performance, enabling a single chip to handle control and computing tasks in scenarios such as robotics and smart gateways that would otherwise require multiple discrete chips.
Regarding the NPU, the EA6530 adopts VeriSilicon's NPU IP, delivering 24 TOPS of INT8 performance and 12 TFLOPS of FP16 performance. Unlike most edge chips that only emphasize INT8 quantization performance, the retention of its FP16 floating-point capability is driven by clear engineering considerations: a large number of vision, point cloud, and semantic models suffer significant accuracy drops when quantized to INT8, and the labor costs of repeated fine-tuning often offset the cost-effectiveness advantages brought by the hardware.
Du Yunhai emphasized that native FP16 support allows algorithm engineers to directly deploy cloud-trained models with negligible accuracy loss, compressing the algorithm porting cycle from weeks to days. This is particularly critical for small and medium-sized solution providers with limited manpower.
"Four-in-One" Integration to Solve System-Level Pain Points
In scenarios such as robotics, edge all-in-one systems, and AI gateways, traditional solutions often resort to a multi-chip patchwork—one chip for motion control, one for navigation, one for visual inference, and one for encoding and decoding. This results in system complexity, high power consumption, and long development cycles.
Addressing this market pain point, Du Yunhai pointed out that the EA6530 integrates the CPU, NPU, VPU (supporting 4K@120fps encoding and decoding and 16-channel 1080P@30fps real-time processing), and a security subsystem into a single chip, providing a four-in-one solution. Four Gigabit Ethernet and four USB 3.0 interfaces cover multi-segment device access, while the physically isolated security subsystem meets the compliance requirements for remote management in industrial scenarios.
This is not a simple stacking of IPs. Instead, it is based on an analysis of the actual usage frequency of edge peripherals, allocating more chip area to compute blocks, streamlining low-frequency interfaces, and delivering more compute resources at the same cost.
RISC-V Ecosystem Maturity is Crossing the Threshold for Practical Deployment
Du Yunhai stated that adopting the RISC-V architecture was still a forward-looking decision when defining the chip in 2023.
Following the complete validation cycle of the EA6530 from tape-out (Q1 2025) to scale deployment (2026), the Tops Microelectronics team reported that RISC-V has basically met the requirements for industrial mass production in terms of toolchain completeness, operating system adaptation, and compatibility with mainstream inference frameworks. Especially in vector computing and custom instructions, the open characteristics of RISC-V leave room for flexible evolution for subsequent chip iterations such as the EA6680 and EA6800, which target perception, comprehension, and physical intelligence.
Deployment is Not Just Chip Delivery, but Capability Transfer
The value of a chip company lies not only in providing chips but also in helping customers complete the last mile from "evaluation" to "mass production." Du Yunhai pointed out that Tops Microelectronics provides layered hardware support ranging from core modules, development boards, and edge AI boxes to AI computing servers, complemented by an AI software stack, NPU toolchain, and Model Zoo, along with algorithm porting and performance optimization services. This "chip + tools + services" combination reduces the most expensive trial-and-error costs in AI deployment.
The market size of Edge AI is expanding at a rate of over 40% annually, yet its penetration rate remains far from saturated. What truly constrains the industry's progress is not the lack of algorithmic advancements, but the absence of a chip that is "just capable enough, just ready to deploy, and just affordable enough."