On July 25, 2026, Thorsianway held a launch event at its new headquarters in Tianjin, officially unveiling the Thor Unified Computing Architecture (TUCA) for next-generation AI and heterogeneous computing, along with its first GPGPU SoC chip for embodied intelligence scenarios, the "Tianheng 1100" (TH1100).
This domestic GPU company, established over a decade ago and previously rarely speaking to the public, has stepped into the spotlight for the first time.
A Decade of Roadmap: From Automotive-Grade MCU to Embodied Intelligence GPGPU
Thorsianway was founded in 2015 by Dr. Xiang Tian and Dr. Wang Pan. The two were undergraduate classmates at the University of Science and Technology of China (USTC) in the class of 2005, and embarked on their GPU entrepreneurship immediately after obtaining their Ph.D. degrees in 2014.
Figure | In 2017, Xiang Tian (second from left), Wang Pan (third from left), and other founding team members of Thorsianway together; Source: Thorsianway
"I was very passionate about working on GPUs during my Ph.D. studies, but the GPU industry was not yet mature at that time, with a shortage of talent. In the market, GPUs were only used as gaming graphics cards, and the capital market struggled to understand the long-term value of general-purpose GPUs," Xiang Tian, founder, chairman, and CTO of Thorsianway, told eefocus reporters.
"In 2015, there was an upgrade demand for LCD and intelligent human-machine interaction interfaces in IoT devices. The transformation of automobiles towards new energy and intelligent connected vehicles brought a critical opportunity. Vehicle mechanical instruments were comprehensively upgraded to LCD instrument panels, but the industry lacked dedicated chips adapted to this scenario. We determined that entering the IoT GPU market starting with LCD instruments for automotive smart cockpits offered threefold advantages: first, it was an industry pioneer with clear track barriers; second, the R&D investment and market entry difficulty were far lower than those of desktop gaming GPUs, with differentiated demands that matched our technical capabilities, resulting in higher feasibility for implementation; third, the market was in an emerging track with rapid growth, and it was easy to expand from automotive-grade products to industrial and consumer-grade markets."
Therefore, Thorsianway initially entered the market through the automotive instrument scenario, launching the world's first automotive-grade MCU with an integrated GPU—the GC9003, which went into mass production in 2019. It was the first domestic automotive-grade MCU capable of running 3D graphics. The company subsequently launched the GC series, including GC9002 and GC9005, and will also introduce the GC9004 to cover rendering and display demands in IoT scenarios such as industrial, automotive, home appliances, medical, and smart hardware. To date, the cumulative shipment has exceeded five million units. Customers include Geely, JAC, Dongfeng, Shaanxi Auto, and TCL, providing the company with stable revenue and experience accumulation in full-chain self-developed GPU IP.
Figure | Milestones of Thorsianway; Source:Thorsianway
Wang Pan, co-founder and general manager of Thorsianway, stated in an interview that the company's technical roadmap has always focused on forward R&D of GPU IP. He likened the company's technology iteration to a building—"Rendering is the first floor, and AI is the second floor." After completing the accumulation of rendering technology from 2021 to 2022, Thorsianway immediately initiated the R&D of GPGPU IP for AI applications. The newly released Tianheng TH series is the natural product of this evolution.
TUCA Architecture Compatible with CUDA, Open Source Lowers Migration Barriers
The Thor Unified Computing Architecture (TUCA) is a full-stack heterogeneous computing platform independently developed by Thorsianway. Benchmarking against NVIDIA CUDA and AMD ROCm, it covers five levels: programming interfaces, compilation optimization, runtime scheduling, acceleration libraries, and ecosystem adaptation.
Figure | Thorsianway releases the Thor Unified Computing Architecture TUCA; Source: Thorsianway
Xiang Tian pointed out that the core design goal of TUCA is to achieve complete mapping of the CUDA API—code written, models trained, and toolchains debugged by developers in the CUDA ecosystem do not need to be rewritten when migrating to Thorsianway chips; they can run after a single compilation.
He revealed in his speech that the engineering team has invested over five years in this effort, completing compatibility adaptation for mainstream computing libraries such as cuBLAS, cuDNN, and cuFFT. Models under the PyTorch and TensorFlow frameworks can be directly deployed.
Regarding this, Wang Pan frankly stated that Thorsianway' solution is currently one of the best in terms of compatibility in China.
In addition, according to the company's product introduction, the core components of TUCA are planned to adopt permissive open-source licenses such as the MIT License, supporting secondary development and commercial distribution.
Addressing the issue of "the pros and cons of open-sourcing the core architecture" triggered by this, Xiang Tian answered: "What is an ecosystem? The ecosystem is human nature; we should try to accommodate human nature as much as possible. IC companies are in the service industry, and open source allows us to better serve customers."
100 TOPS, 128GB Memory, TH1100 Targets Edge AI Inference
The TH1100 is Thorsianway' first GPGPU SoC targeting edge AI inference scenarios such as embodied intelligence. It integrates six self-developed SXGPU cores and an 8-core Cortex-A55 CPU, along with an integrated ISP and security encryption engine. Its FP4 sparse computing power reaches 98.2 TOPS, and FP16 dense computing power is 12.3 TFLOPS, supporting multiple precisions including FP32, FP16, FP8, INT8, INT4, and FP4.
Figure | Thorsianway releases its first GPGPU product, TH1100; Source: Thorsianway
The TH1100 memory subsystem supports up to 128GB capacity with a bandwidth of 85.3GB/s. A single chip can handle full inference of 35B-A3B parameter-level large language models, while meeting the memory demands of long-sequence KV Cache and multi-task concurrency. Taking the deployment of the Qwen large model in humanoid robot scenarios as an example, the TH1100 can achieve an inference latency of approximately 50 milliseconds per token at INT4 precision. This means it can enable highly smooth real-time dialogue and human-machine interaction without any perceptible delay.
The TH1100 also supports GDB source-level GPU debugging, Profiler performance analysis, SMI system call interfaces, as well as multi-task parallel computing and priority preemption scheduling. In terms of interfaces, the TH1100 is equipped with 4 channels of 4-lane MIPI CSI, 1 channel of 4-lane MIPI DSI, and 6 channels of Gigabit Ethernet. It supports Secure Boot and hardware encryption, adapting to scenarios such as robotics, industrial inspection, autonomous driving, and smart healthcare.
Regarding product strategy, Xiang Tian revealed that Thorsianway adopts a pace of "mass-producing lower computing power first, followed by higher computing power":
- Targeting scenarios such as embodied intelligence and smart medical services, the TH1100 (100 TOPS computing power) will be deployed in 2026;
- Targeting scenarios such as high-performance robotics and autonomous driving domain controllers, the TH1800 (800 TOPS computing power), benchmarking against Jetson Thor, is planned for tape-out by the end of 2027;
- Targeting high-end autonomous driving and all-in-one machine scenarios, the TH24K0 (4000 TOPS computing power), benchmarking against RTX 4090, is planned for mass production in 2028.
Technical Feature: Conservative in Ecosystem, Aggressive in Devices
In terms of technical roadmap, Thorsianway exhibits a "dual nature": it chooses a conservative approach at the architecture level, insisting on CUDA compatibility to avoid increasing developers' learning costs; however, it is relatively aggressive at the semiconductor device and process level.
Regarding this, Xiang Tian stated that under the constraints of limited process nodes, performance improvement needs to shift towards deep collaborative optimization of devices and architecture, namely compressing signal latency at the underlying levels such as transistors and interconnects, and reducing the energy consumption of data movement.
The company is advancing two self-developed innovations: first, using a digital compute-in-memory design approach to integrate storage and computing within the standard cells of the GPU IP, achieving a reduction in data movement inside the IP; second, developing AI ROM technology to solidify large model parameters into the ROM inside the GPU chip, with the goal of increasing storage density by more than an order of magnitude compared to HBM, fundamentally reducing storage costs for edge deployment and improving token output efficiency.
Explaining this, Wang Pan said: "The industry has long faced the memory wall bottleneck. Large models have massive parameter counts, placing extremely high demands on storage capacity and data movement bandwidth, resulting in enormous data movement overhead. ROM is not a new technology; its read and write speeds are inherently superior to storage solutions like DDR, and it was previously only used to store small programs such as boot guides and fault recovery. Our core idea is to treat the weight parameters of large models as 'super-large boot firmware' for AI chips, upgrading traditional small-capacity ROM to high-density, large-capacity on-chip ROM, integrating it with the GPU in a unified design, and ensuring compatibility with existing mature manufacturing processes. This is also the key R&D direction we are focusing on at this stage."
Regarding the drawback raised by reporters that ROM cannot be repeatedly programmed, affecting upgrades, Wang Pan stated: "In practical applications, the chip completes tape-out first, and the GPU with AI ROM is already manufactured, with no data in the ROM. When the terminal demands of embodied intelligence manufacturers are clear, customers will send us the confirmed parameters, which are programmed into the AI ROM using specially developed EBL equipment and provided to the customers. If the parameters change for the next batch, they can be sent to us again to directly program a new batch of chips. The model is upgraded inside the GPU at any time, and the cycle and cost are far lower than redesigning and tape-out a new chip. In most scenarios, the parameters accompany the device throughout its lifespan. Chips with this solution will save a large amount of costs for high-performance storage like HBM, and have a token rate nearly an order of magnitude faster. For scenarios with subsequent upgrade demands for parameters, while using the AI ROM solution, a smaller capacity of HBM will also be equipped to store the changing parameter parts, and software will be used to synthesize parameter changes during use."
Building on this, he further revealed that the next-generation Tianheng chip will achieve single-chip deployment of large models on the scale of DeepSeek-V4-Flash.
Orthodontic All-in-One Machine Shipped, Strategic Agreements Signed with DeepCybo and CIQTEK
At the launch event, Thorsianway showcased the smart orthodontic all-in-one machine developed based on the TH1100—a medical AI workstation with locally deployed data, capable of completing the closed-loop process from patient file creation, image uploading, AI report generation, to consumable order sending.
Figure | Xiang Tian demonstrating the smart orthodontic all-in-one machine developed based on TH1100; Source: Thorsianway
Xiang Tian revealed that this smart orthodontic all-in-one machine product has entered the stage of mass shipment.
Meanwhile, Thorsianway signed strategic cooperation agreements with DeepCybo (a physical AI enterprise) and CIQTEK (a high-end instrument and equipment enterprise). The former will rely on Thorsianway' GPU computing power to promote the industrialization of physical AI; the latter will carry out joint R&D in the field of high-end electron beam instruments centered around AI ROM technology.
Headquarters Relocated to Tianjin, the Starting Point for the Next Decade
On the same day, Thorsianway announced the relocation of its headquarters to Jinnan District, Tianjin.
Figure | Thorsianway headquarters settled in Jinnan District, Tianjin; Source: Thorsianway
Xiang Tian stated that Tianjin's 2026 Government Work Report proposed the "Jinmen Embodied Action Plan," and Jinnan District is home to Tianjin University and Nankai University, with dense intellectual resources. Returning to Tianjin is a decision that combines the right timing, favorable geography, and harmonious people. The company plans to advance IPO cultivation and local industrial construction simultaneously, leveraging Jinnan District's integrated circuit industrial policies and university talent resources to lay a solid foundation for the next decade.
Discussing the competitive landscape, Wang Pan stated in the interview: "We are not targeting any domestic companies. Our starting goal is to catch up with NVIDIA and strive to close the gap and catch up with them as soon as possible."
In their view, the ultimate competition for edge AI chips lies in the ability to achieve a closed-loop business model—which is precisely the differentiated advantage accumulated by Thorsianway through a decade of to-B services.