Author: Feng Ning
In the first week of September 2026, two pieces of news invigorated the entire memory chip industry.
01. 3D DRAM: A Clash of Giants
Recently, at an internal technical seminar, AMD disclosed exciting experimental data: a 3D DRAM architecture based on Hybrid Bonding technology can improve energy efficiency by up to 17 times compared to traditional HBM stacks. This means that under the same power consumption, data transmission efficiency can achieve an order-of-magnitude leap.
Although traditional HBM vertically stacks DRAM chips through TSV (Through-Silicon Vias), the chips still rely on microbumps for connection. These tiny solder balls create physical gaps during connection, which must be filled with liquid plastic underfill. This brings about issues such as parasitic resistance, limited connection density, and hindered heat dissipation.
The Hybrid Bonding 3D DRAM proposed by AMD completely revolutionizes this design. It stacks DRAM chips directly on top of the XPU (processor or accelerator), eliminating the bottleneck caused by traditional PHY interfaces. In terms of process, it abandons microbumps, directly polishing the wafer to atomic-level flatness, allowing copper to fuse directly with copper upon heating (Cu-Cu bonding).
The advantages of 3D DRAM extend far beyond energy efficiency. Placing DRAM directly above the compute chip significantly shortens the physical distance for data movement. In AI accelerators, data movement consumes a massive amount of energy; shortening this distance can directly reduce power consumption.
Coincidentally, NAURA, a leading domestic semiconductor equipment manufacturer, recently published an academic paper in an IEEE journal, announcing a major technological breakthrough in the manufacturing process of 3D DRAM, the next-generation memory chip. The company has developed an innovative "two-step cyclic etching process" specifically targeting a 64-layer alternating stack structure of silicon and silicon germanium, achieving a structural uniformity of over 95%.
According to the data disclosed in the paper, this process achieves a silicon germanium-to-silicon etching selectivity ratio of over 500:1. In a 200-nanometer interlayer structure, the single-pass loss of the silicon layer is controlled within 10 angstroms (1 nanometer).
Industry analysts believe that if domestic DRAM leaders can integrate NAURA's domestically produced etching equipment and related processes, it will significantly enhance the feasibility of evolving towards independent mass production of 3D DRAM.
As these two pieces of news stir up the entire memory chip industry, one cannot help but ask: Why exactly has 3D DRAM become the focal point of competition among global chip giants?
02. Why is 3D DRAM So Highly Anticipated?
To understand the value of 3D DRAM, one must first recognize the "ceiling" that traditional DRAM is approaching.
For a long time, the DRAM industry has followed a path similar to that of logic chips—continuously improving memory density by shrinking process nodes. However, as line widths approach below 10 nanometers, physical limits begin to emerge. Unlike processors, DRAM memory chips must rely on capacitors to store data. As process nodes continue to shrink, it becomes difficult to further reduce the size of capacitors, and the reduced spacing between transistors increases the risk of short circuits. The high cost and export controls of EUV (Extreme Ultraviolet) Lithography machines have further nearly closed this path for some players.
The core concept of 3D DRAM is to shift transistors from traditional 2D planar scaling to 3D vertical stacking, increasing memory cell density by stacking transistors layer by layer. In simple terms, since they can no longer fit lying "flat," they must "stand up"—arranging memory cells vertically rather than horizontally, thereby making more efficient use of the internal space of the chip.
Currently, there are two main routes for 3D DRAM. One is 4F² VCT (Vertical Channel Transistor) DRAM; the other is VS-CAT (Vertical Stacked-Cell Array Transistor) DRAM.
The core of the former is "standing upright," mainly developing in the z-direction for the DRAM cell structure, while the core of the latter is stacking, stacking multiple layers of DRAM similar to 3D NAND, which is also understood as true 3D DRAM.
The size of DRAM cells is compared based on the design rule (or minimum feature size) "F: feature size." In the 2010s, by improving the layout of the DRAM cell array, the cell area was reduced from the traditional "8F²" to "6F²." Even with the same feature size, the cell area was reduced by 25%.
Subsequently, as the 6F² architecture once again gradually approaches the physical limit, 4F², as the theoretical density limit of 2D planar layout, has become an inevitable choice to continue Moore's Law. Theoretically, on a chip of the same size, the 4F² architecture can integrate 30% to 50% more memory cells than the 6F² architecture, directly translating to higher storage capacity, faster data throughput, and lower operating power consumption.
The three major memory giants mostly adopt a dual-track layout strategy, that is, while deploying 4F² VCT, they are also developing VS-CAT. However, the "terminology" used by each company varies greatly.
Let's first look at Samsung's approach. Samsung's VCT technology vertically erects the transistor channel, increasing the channel length within a limited chip area, effectively mitigating the short-channel effect and leakage issues encountered by traditional planar transistors during scaling. On the other hand, Samsung has adopted wafer-to-wafer hybrid copper bonding technology, manufacturing the memory cell array and peripheral circuits on different wafers and then vertically stacking them to achieve ultra-high-density interconnection. The channel material has also been changed from traditional silicon to Indium Gallium Zinc Oxide (IGZO) to suppress leakage current in scaled-down cells.
According to Samsung's plan: complete the R&D of 10a process DRAM this year, conduct quality testing next year, and introduce it into mass production lines in 2028. It is reported that Samsung plans to continuously apply the two core technologies of 4F² square cells and VCT to three generations of processes: 10a, 10b, and 10c; starting from the 10d node, it will fully transition to a 3D stacked DRAM architecture.
In the true 3D stage, Samsung's layout is more aggressive. It is reported that Samsung Electronics has currently achieved 16-layer stacked VS-CAT DRAM internally. In addition to increasing capacity through stacking, VS-CAT DRAM can also reduce current interference. Samsung Electronics expects it to adopt a dual-wafer structure with separated memory cells and peripheral logic units, because continuing the traditional single-wafer design would bring severe area overhead. After completing the production of the memory cell wafer and the logic unit wafer separately, wafer-to-wafer (W2W) hybrid bonding is required to obtain the final VS-CAT DRAM product.
SK Hynix's route is highly similar to Samsung's in strategic logic, but there are differences in technical naming and implementation details. SK Hynix refers to its 4F² structure as Vertical Gate (VG), rather than the VCT used by Samsung.
At the 2025 IEEE VLSI Symposium, SK Hynix CTO Cha Seon Yong explicitly stated that the 4F² VG platform and 3D DRAM technology will be applied to 10-nanometer-class and below nodes to overcome the scaling limitations of existing technology platforms. The core feature of VG is that the gate is placed vertically and surrounds the channel, forming a fundamental difference from the traditional structure with horizontal gates.
In the 3D stacking stage, SK Hynix's layout is equally active. It is reported that SK Hynix is accelerating the development of 3D stacked DRAM technology and has launched recruitment for related engineering talents, simultaneously conducting joint chip design work with US customers. Recently, SK Hynix stated that the development of next-generation memory 3D DRAM semiconductors can utilize foundry processes. In addition, SK Hynix is exploring the use of IGZO oxide semiconductors as next-generation channel materials, utilizing their low-temperature deposition characteristics to solve the thermal budget issues in 3D stacking.
Micron started its research on 3D DRAM as early as 2019. According to statistics from TechInsights, by August 2022, Micron had obtained more than 30 3D DRAM patents, while Samsung Electronics held 15 patents, and SK Hynix held about 10 patents. It can be seen that the number of Micron's 3D DRAM-related patents is 2 to 3 times that of these two South Korean memory chip giants. However, regarding mass production actions, there has been no news from Micron. Furthermore, on the issue of introducing 4F² Memory Cells, Micron has also shown an ambiguous and mysterious attitude.
03. Equipment Industry: Shift in Focus
Returning to the beginning of the article, the Hybrid Bonding technology developed by AMD for the 3D DRAM solution follows the stacking route between bare dies, i.e., Die-to-Die.
However, the 3D DRAM process breakthrough disclosed by NAURA in the IEEE conference paper may focus more on the monolithic integrated vertical stacking route within a single wafer, rather than the D2D bonding and packaging stacking solution between multiple chip dies.
As is well known, lateral selective etching under high aspect ratio structures has always been an industry challenge. In simple terms, you need to precisely etch away one layer among dozens of alternately stacked materials without damaging the adjacent layers. This is like pulling out one sheet of paper from a stack without tearing the adjacent sheets above and below. If the process is not up to standard, either the etching selectivity is insufficient, causing damage to the silicon skeleton, or the micro-loading effect causes the accumulation of bottom reaction products, which in turn leads to severe unevenness in interlayer etching, causing a sharp drop in the yield of the entire chip.
NAURA's two-step cyclic etching technology divides the process into two iterative stages: etching and cleaning. The first stage uses unbiased electrically neutral fluorine radicals for targeted etching of the silicon germanium layer, showing extremely high selectivity to silicon, and forming a dense germanium fluoride protective film on the surface of the silicon layer. The second stage then introduces reactive gases to clean the deposition of bottom by-products, ensuring the smooth penetration of etching gases in the vertical direction.
The significance of NAURA's process breakthrough this time must be viewed in the context of the situation of domestic DRAM.
Before EUV, DRAM mainly used 193nm immersion DUV lithography machines. Below 20nm, single exposure of DUV can no longer draw fine patterns, and multiple patterning must be adopted to "piece together" circuits through multiple exposures and etching. This method can continue to scale down to 1x nm, but it involves many steps, high costs, and difficult yield control.
When the cost of multiple patterning approaches its limit, EUV begins to take the stage. The wavelength of EUV is 13.5nm, with a resolution far higher than that of DUV. In 2020, Samsung took the lead in shipping 10nm-class D1x DDR4 based on EUV, and subsequently fully introduced EUV at the D1a node. Later, SK Hynix and Micron followed suit. The core reason for switching to EUV is that it can reduce multiple patterning steps, simplify the process, increase capacity, and break through the resolution bottleneck of DUV.
As DRAM continues to advance to the 1δ node and below, traditional EUV is also approaching its limit, making High-NA EUV the next stop.
In August 2026, Samsung Electronics publicly committed at the NGL 2026 Next Generation Lithography conference: for A10 (1nm) and below DRAM process nodes, High-NA EUV technology must be introduced, with formal introduction into mass production lines in 2030.
At the same time, a vice president of SK Hynix announced at the same conference that the company has fully launched High-NA EUV R&D and simultaneously introduced PSM (Phase Shift Mask) — a mask material that can control both light intensity and light phase simultaneously, used to suppress diffraction artifacts and truly release the theoretical resolution of High-NA EUV.
The two roadmaps point to the same conclusion: the process evolution of next-generation DRAM will completely bid farewell to the path of the past decade of "forcing scaling by stacking EUV exposure layers," and turn to a new stage where the number of exposure layers does not rise but falls, node naming aligns with logic chips, but the mass production pace is deliberately lagging by 2-3 years.
Domestic manufacturers' exploration in the field of 3D DRAM is not limited to etching.
According to a search on the website of the China National Intellectual Property Administration, a leading domestic 3D NAND manufacturer applied for a DRAM patent with an Xtacking architecture as early as 2020. The Xtacking architecture is the company's unique architecture for producing its 3D NAND memory, adopting a 3D wafer hybrid bonding process. According to the patent description, the DRAM memory with the Xtacking architecture includes a first wafer having array transistors formed therein, a second wafer having capacitor structures formed therein, and a bonding interface formed between the first wafer and the second wafer including a plurality of bonding structures.
The team of Academician Liu Ming at the Institute of Microelectronics, Chinese Academy of Sciences, based on the vertical annular channel structure IGZO FET, studied the impact of the interlayer dielectric process before the stacking of the second layer of devices, verified the reliability of CAA IGZO FET in 2T0C DRAM applications, and helped promote the realization of 4F² IGZO 2T0C-DRAM cells.
First NAND moved to 3D, and subsequently DRAM and advanced logic chips are all developing in this direction. Against this backdrop, in addition to high aspect ratio etching technology, processes such as Atomic Layer Deposition (ALD) and Hybrid Bonding are simultaneously ushering in an explosion period.
During the recent 14th Semiconductor Equipment and Materials Core Components Exhibition (CSEAC 2026), AMEC launched multiple newly independently developed high-end micro-processing equipment, covering key tracks such as ultra-high aspect ratio etching, Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), metal thin film deposition, and silicon carbide epitaxy. This is another high-density concentrated debut of new products by AMEC within half a year, following the release of four new products at SEMICON China in March this year.
As a leading domestic thin film deposition equipment manufacturer, Piotech has a natural technological synergy advantage in expanding into the hybrid bonding field. Its developed Dione 300 series Wafer-to-Wafer (W2W) bonding equipment can achieve high-precision bonding of multi-material surfaces at room temperature, and is widely used in fields such as 3D IC, Advanced Packaging, and CIS. HWATSING is one of the few domestic manufacturers capable of mass-producing CMP (Chemical Mechanical Polishing) equipment. CMP is a critical process step in chip manufacturing, directly affecting the flatness and yield of the chip. ACM Research supplies cleaning equipment to domestic memory leaders; Jingce Electronic provides optical inspection and metrology equipment; Kingsemi is a coating and developing equipment supplier; Zhizhida focuses on memory chip testing equipment; Zhichun Technology provides high-purity process systems, etc.
The competition in 3D DRAM is, in essence, a huge gamble on the future form of memory chips. From the dual-track layout of Samsung and SK Hynix, to Micron's patent accumulation, and then to NAURA's breakthrough in etching processes, the upstream and downstream of the industry chain are being dragged into this transformation simultaneously. The winner is not yet clear, but the direction is already clear: the next decade of DRAM will be a decade of "standing up."