Author: Peng Zhao (Founder of Zhicifang, Co-Founding Partner of Yunhe Capital) Original
On August 6, SpaceX announced a joint initial investment of $16.8 billion with Tesla to build the Terafab chip manufacturing facility in Texas. The official annual production capacity target is over 1 terawatt of computing power, an astonishing figure. According to Musk, the current global annual AI computing capacity is about 20 gigawatts, making 1 terawatt roughly 50 times that amount. In terms of chip units, the plan targets an annual production of 100 billion to 200 billion AI and memory chips.
To provide a more intuitive sense of scale, consider this analogy: the planned total construction area of this facility is equivalent to 1,700 standard American football fields, or the combined size of 10 Tesla Gigafactories in Texas. At full capacity, the computing scale will be sufficient to simultaneously support the full-load operation of millions of super AI servers or over 100 million embodied intelligence devices. The official announcement did not specify a production start date, but Phase I is reported to be planned for production in the second half of 2027, with the first batch of chips mass-produced in 2028.
Prior to the announcement of this grand plan, if we rewind the timeline by another three weeks, Tesla's AI5 chip completed tape-out on Samsung's 2nm process, and the dual-foundry (TSMC (Taiwan Semiconductor Manufacturing Company) + Samsung) adaptation was fully realized. The tape-out of this chip was announced on April 15 this year, with large-scale mass production expected in 2027.
If we look at the customer list for AI5 or the capacity allocation table for Terafab, the term "AIoT" cannot be found, because AIoT terminal and solution companies rarely engage in the in-house R&D of underlying chips.
Cellular modules rely on the scale of smartphone baseband chips to amortize costs, edge computing boxes rely on automotive and robotics chips to amortize costs, and MCUs (Microcontroller Units) rely on automotive-grade and industrial applications to amortize costs... The AIoT is the largest long-tail audience in the "open market for general-purpose chips."
However, "closed-loop in-house chips" like Tesla's AI5 are transforming chips from clearly priced general-purpose commodities into "native organs" within corporate ecosystems. For the AIoT industry, this involves a deep logical evolution; the open market has not only lost a super buyer but also lacks a critical underlying price anchor.
A question of widespread concern in the industry is whether AI5 can be deployed in a broader range of edge devices. Musk's attitude is very clear: although AI5 possesses data center-level training capabilities, its core architecture is extremely optimized for advanced edge computing scenarios such as Optimus (humanoid robots) and Robotaxi (autonomous robotaxis).
As one of the most aggressively optimized chips globally for "edge inference," the specification sheet of AI5 may well be a window into the future of the AIoT industry.
From "TOPS-Only" to "Memory is King"
For a long time, the "core yardstick" for evaluating edge device performance in the AIoT industry has been "TOPS" (the unit of processor computing power). However, TOPS is actually the language of the supply side, measuring only "how much logical computing power a chip can provide"; whereas "memory" is the language of the workload side, determining "how fast actual tasks can run."
In the past, edge devices ran small-model visual tasks, where the core bottleneck was computing power. Today, however, the introduction of multimodal and edge-side large models (such as VLMs, Vision-Language Models) is shifting high-end edge workloads to be memory-constrained.
The specification sheet of AI5 is the developer of this "bottleneck shift." Direct evidence is Tesla's transition solution: the AI 4.1 chip, designed to extend the life of its cars, features doubled memory and higher bandwidth, but only about a 10% improvement in computing performance. A vertically integrated company that consistently starts from first principles only adds to its own products when something is lacking.
Moving to the flagship AI5, the structure of resource allocation is even clearer. According to the disclosure during the tape-out announcement, the comprehensive performance of AI5 is 40 times that of AI4, with raw computing power increasing 8 times, memory capacity expanding 9 times (from about 16GB to 144GB), and bandwidth approximately 5 times that of the previous generation (1.9TB/s), specifically optimized for the Transformer engine. The memory increase exceeds the computing power increase; the gap between the 40-fold comprehensive performance and the 8-fold raw computing power is exactly the space contributed by memory, data pathways, and architecture. In other words, the bulk of the comprehensive performance comes from beyond raw computing power.
The next generation continues to raise the stakes. Musk stated that the latest FSD has pushed the AI4 memory to its limit, and the future AI6 will even pair nearly half of its AI accelerators directly with high-speed onboard SRAM memory.
For three consecutive generations of products, resources have been entirely tilted toward the memory side.
When edge-side large models begin to be deployed on edge devices, computing units often wait for data movement, leading to idle computing power. Breaking the "memory wall" has become critical for edge AI. Massively stacking memory capacity and bandwidth is essentially aimed at reducing the extremely high power consumption and latency caused by data movement. This sends a strong signal to the entire AIoT industry: the focus of future edge intelligence will no longer be on simply stacking logical computing units, but on how to solve storage and data throughput issues at the lowest cost.
This trend has actually been quietly written into the financial statements of AIoT companies themselves.
The income statement records the pain of price increases. MeiG Smart's 2025 annual report disclosed that its gross profit margin of main business dropped by 3.47 percentage points year-on-year, attributing one of the reasons to "cyclical price increases in memory chips." The balance sheet records concerns about the future. MeiG Smart's inventory increased by 30.36% year-on-year, explicitly including strategic stockpiling of memory chips; Quectel's inventory increased by 69.48% year-on-year, explained as "increasing stockpiling and material preparation to cope with future sales growth, shortages of some raw materials, and price increases"; Fibocom also listed memory chips as a risk of price fluctuation in core raw materials.
When companies begin to accumulate balance sheets for a single material, it indicates that memory is transforming from a "bulk material" procured according to market conditions into a "strategic material" that determines whether terminal large models can be successfully deployed.
The Battle for the Computing Power Base: Ecological Niche Determines the Hardware Ceiling
Tesla's ability to spend heavily on in-house chip R&D is by no means solely due to the order volume accumulated from robots or cars. In Terafab's capacity planning, Musk's rough estimate in August is that about 3/4 of the computing power will be used for space AI and spacecraft, and about 1/4 allocated to hardware such as Tesla robots.
However, more core than scale is the quality of its "computing power base." The multi-dimensional demands within the Musk system (Tesla's cars and robots, ground supercomputers, SpaceX's orbital computing power) highly share the same architectural lineage and software stack, with vision-centric multimodal real-time inference as their common denominator. A chip with the same underlying architecture can almost penetrate all scenarios, constituting a highly intensive "homogeneous computing base."
In contrast, fragmentation is ingrained in the genes of the AIoT industry. The computing base aggregated at the module layer in the industry is a mix of smart water meters, automotive cockpits, robotic lawnmowers, AR glasses, and other devices. These computing workloads, which lack underlying connections with each other, constitute an extremely fragmented "heterogeneous computing base."
A homogeneous computing base is sufficient to support a multi-billion-dollar closed loop of in-house chip R&D, whereas the commercial ceiling of a heterogeneous computing base often remains confined to centralized procurement and solution reuse.
Therefore, for the vast majority of AIoT companies, "whether to develop chips in-house" is a false proposition. The life-or-death question is, which large "computing power ecosystem camp" should we align with? And what ecological niche should we occupy within it?
In China, samples that have crossed this threshold already exist. Huawei uses its in-house chips to simultaneously support mobile phone, automotive, and IoT (Internet of Things) workloads, though its constraints lie on the manufacturing end rather than the demand end. An observation target still near the threshold is Xiaomi's human-car-home ecosystem; the device scale may have met the standard, but the degree of workload homogenization is questionable.
For the broader AIoT companies, the "computing power aggregators" in the real market are actually the major module enterprises.
Data from the 2025 annual reports show that the business radius of module companies has comprehensively expanded from traditional "communication connectivity" to "edge computing." Fibocom has upgraded AI modules to a formal category, with the Nebula series laying out a full computing power matrix from 1T to 50T; Quectel has built a "1+N" matrix, planning smart modules of 100 TOPS and above for 2026; MeiG Smart's high-computing modules of nearly 80 TOPS are also under research, and its modules are defined as "computing power hosting platforms that provide terminal-side and edge-side computing capabilities for various IoT terminals."
Module manufacturers are aggregating tens of thousands of fragmented demands into bargaining chips sufficient to negotiate and bargain with upstream chip original manufacturers. And this aggregation is reflected not only in hardware procurement but, more importantly, in the premium pricing capability of hardware-software collaboration.
Fibocom's solution revenue reached 476 million RMB, an increase of 133.36%. This figure points to the direction of the shift in pricing power; it is the solutions matched to scenarios that truly price "AI's judgment capability."
Therefore, when terminal device companies choose module suppliers, their evaluation logic should also be reconstructed. They can no longer simply focus on hardware BOM costs and unit prices, but should focus on evaluating the supplier's comprehensive solution capabilities. Can they democratize high-end computing power, bringing it down to a cost range affordable for AIoT devices? More importantly, can their integrated hardware-software solutions deeply understand and adapt to vertical scenarios, thereby significantly lowering the threshold for secondary development?
Combating "Intelligence Depreciation": Computing Power Decoupling and Edge Architecture Reconstruction
In addition to supply chain fluctuations, we must also face a more thorny industrial contradiction: the divergence in depreciation curves between underlying computing power and terminal devices.
Currently, the iteration speed of AI chips is evolving at multiples of Moore's Law. NVIDIA maintains a "once-a-year" release pace, while Tesla's stated goal is a 9-month chip design cycle.
However, the lifecycle of AIoT devices is completely different. According to common industry practice, a smart water meter or power grid monitoring device is typically depreciated over ten years, the service life of industrial gateways is often over eight years, and even consumer-grade embodied intelligence devices require a lifespan of three to five years.
Chips are replaced every year, while devices are scrapped every ten years.
If the traditional integrated hardware-software packaging model continues to be used, it means devices will be outdated right out of the factory, and their built-in "intelligence content" will depreciate rapidly on a quarterly basis. When multimodal large models are upgrading by leaps and bounds every year, relying solely on software-level OTA (Over-The-Air) updates can no longer make up for the physical bottlenecks of hardware computing power and memory.
This bifurcation and misalignment of depreciation curves may force a fundamental transformation in AIoT hardware architecture: "computing power decoupling" and "modular pluggability" may evolve from a geeky engineering preference into a hard requirement for enterprise asset management.
Future smart modules need to be capable of independent upgrading and replacement throughout the entire lifecycle of the device. Otherwise, the residual value of the entire high-value device will rapidly drop to zero as the old chip inside becomes obsolete.
The "computing power card" product disclosed in Quectel's annual report is precisely an early form of this trend. We can foresee that in the future, module companies may no longer deliver SoCs (Systems on Chip) soldered onto motherboards, but rather standardized "computing power slots" and continuously iterating computing power subscription services.
This is not only a change in hardware form but also a transformation of AIoT companies' capital expenditures (CapEx) into more flexible operational expenditures (OpEx).
In Conclusion
Musk's chip manufacturing and the construction of Terafab cannot be merely viewed as stories or news in the semiconductor circle; it is a clear mirror reflecting the underlying logic of the future AIoT industry.
From the moment AI5 was designed to prioritize serving robots, the focus of AIoT has already pointed toward operation and decision-making. As the interaction between devices and the physical world becomes exceptionally complex, the reconstruction of edge-side computing power and architecture has become an irreversible industrial trend.