Agent workloads are shifting the CPU-to-GPU ratio in AI servers from the training-era standard of 1:8 toward 1:1, driving a multiplicative expansion in host-side memory and storage demand. Constrained by HBM production bottlenecks and the high premiums on large-capacity DDR5 modules, the competitive focus in AI storage is moving from single-layer high-speed video memory to cross-tier coordination among HBM, host memory, CXL, and enterprise SSDs. Google has leveraged TPU Sync to establish low-loss cache offloading channels, while Intel uses hardware-level CXL scheduling and processor memory expansion to help cloud providers mitigate capacity cost pressures.
However, the spillover of demand to the host side has not delivered universal benefits downstream. Hyperscale cloud vendors are simultaneously reclaiming hardware definition rights. Leading domestic cloud providers are shifting to direct procurement of original NAND flash wafers, commissioning white-label customization, and advancing self-developed controllers. This forces independent drive manufacturers like DapuStor to pivot from earning margins on standard hardware to capturing returns from firmware tuning and custom services. Upstream, Montage Technology was the first to secure positions in global CXL controllers and new memory companion chips, but short-term volume growth is constrained by server CPU shortages and new platform transition schedules. Meanwhile, CXMT and YMTC are accelerating their lock-in of the domestic data center foundation by capitalizing on supply gaps left by overseas manufacturers prioritizing HBM, while simultaneously facing cyclical divergence between high consumer inventory levels and spot price declines.
A deep dive into Q3 2026 cash flow reports and changes in cloud vendor procurement reveals that the general module model—relying on hoarding wafers at lows to capture price spreads—is failing in the data center market. Long-term returns are increasingly concentrating on two types of Chinese companies: manufacturing fabs holding scarce wafer capacity, and interconnect chip, controller, and custom firmware vendors embedded in the data paths of large-scale AI systems.
Introduction
On November 9, 2026, two Silicon Valley computing giants independently took actions that broke industry inertia. For years, the computing industry’s obsession was stuffing more data into HBM video memory closest to the compute cores. But on that day, alongside launching the dual-chip inference system TPU 8i Max and significantly increasing single-package HBM bandwidth, Google specifically open-sourced the TPU Sync framework, striving to move conversation caches (KV Cache) generated during inference out of the chip to host memory and hard drives. Almost simultaneously, Intel unveiled its next-generation Xeon CXL flat memory solution, using external extended memory to support hundreds or thousands of concurrently running Agent sandboxes.
Why are giants suddenly rushing to "move data outward" when video memory bandwidth is still setting records? Tracing this trajectory of data migration reveals not just a technical architecture shift, but a quiet redistribution of interests within China's storage supply chain. Water is indeed overflowing from the expensive HBM pool, but not all companies positioned downstream can catch this wave of benefits.
I. Why Does AI Suddenly Need More Storage Beyond HBM?
The trigger for computing giants to "move house" is that large models have evolved from single-turn Q&A to long-cycle online Agents, making data center cost calculations unsustainable. In traditional training clusters, pairing 1 CPU with 8 GPUs was the standard configuration. However, once Agents run, the system frequently calls external tools, executes code in sandboxes, and reviews historical sessions spanning days. Compute cards spend nearly half their time waiting for external responses. A massive influx of unstructured processing and scheduling tasks flows back to the host, pushing the internal CPU-to-GPU ratio in servers to converge rapidly toward 1:2 or even 1:1. The required CPU and memory channels on the host can expand up to eightfold. Operational accounts from a leading domestic cloud provider confirm this chain reaction: for every CNY 1 spent by customers on AI cloud services, an additional CNY 0.5 to 1.5 in general CPU cloud, memory, and storage consumption follows four to five months later. Robust host demand has even stretched delivery times for Intel and AMD server CPUs to 6–24 months.
Expensive HBM cannot accommodate these dormant sessions in a waiting state, nor is it worth locking them there long-term. The only solution is to reposition data based on temperature: extremely hot data performing first-token computation stays in HBM; warm sessions suspended for seconds to minutes and concurrent sandboxes retreat to host DDR5 or CXL extended memory (CXL is not a fourth storage medium but a bridge for connecting and scheduling memory, capable of hanging new memory or being compatible with old memory); long conversation records retained across days and retrieval knowledge bases sink further into enterprise SSDs.
But engineers quickly hit the first physical constraint when sinking data to hard drives: NAND flash particles have a limited erase-write lifespan. If fragmented conversation caches are written directly to hard drives without organization, they will exhaust an enterprise SSD's lifespan in about four months, resulting in hardware depreciation costs higher than simply letting the GPU recalculate. Therefore, only long-context, long-suspended data aggregated into large sequential writes makes economic sense on high-performance enterprise drives. Ultra-high-capacity QLC drives with lower endurance must strictly handle static corpus and cold data archiving. The question arises: since data migration fears both slowness and high costs, how do computing giants build this channel?
II. Why Are Google and Intel Taking Different Technical Paths?
Facing the same dilemma but trapped in different supply chain bottlenecks, Google and Intel each solved half of the engineering challenge: one focused on moving data out with low loss, the other on enabling hosts to store it at low cost.
Google's reality is that compute chip production expansion is blocked, forcing them to seek space through system transport efficiency. Supply chain research indicates unexpected delays in next-gen chip samples handled by external low-cost partners, while HBM and advanced packaging tightly constrain front-end wafer input scale. Unable to rapidly deploy new compute dies, Google chose to co-package two mature inference chips into the TPU 8i Max, while using TPU Sync to remove the biggest barrier to data leaving the card. Previously, offloading cache to host memory consumed over 60% of the time in CPU data format rearrangement; now, data maintains its original layout and goes straight to main memory, reducing offload latency by up to 90% (currently, mass production is concentrated on HBM-to-host-memory, with overflow to SSDs still in experimental stages). This year, Google even extended its custom chip collaboration with Marvell to storage controllers and memory interface controllers.
Intel targets another pain point on cloud vendors' purchase orders: excessive premiums on high-capacity memory sticks. As state data floods the host, non-HBM memory procurement needs for a major North American cloud provider alone will jump from 1.53 EB this year to over 2.3 EB next year. Yet in the procurement market, the long-term contract price for a 64GB DDR5 stick remains around USD 900, while spot quotes for scarce 128GB high-capacity modules soar to USD 2,600–2,800. The unit cost of buying single high-capacity modules is more than 50% higher than installing two medium-capacity ones. To help cloud vendors bypass sky-high modules and install more sandboxes per machine, Intel hardened hot/cold page scheduling into the CPU internals, suppressing long-tail latency losses for external CXL memory to under 2%; meanwhile, on the delayed next-gen flagship processor (Diamond Rapids), Intel significantly raised the default memory configuration per socket from the originally planned 8–12 sticks to 16.
Google pulled the data out, Intel expanded the host slots, and budgets originally concentrated in HBM naturally flowed to enterprise SSDs and host memory interconnects. At this point in the story, downstream storage vendors should seemingly be lining up for orders—but upon entering the real procurement negotiation tables of cloud giants, the script takes a turn.
III. Can Chinese Enterprise SSDs Catch This Demand Wave?
Demand did land on enterprise SSDs, but savvy hyperscale cloud vendors do not intend to pay premiums for standard brand drives. As cloud giants push "white-label direct procurement" and "self-developed controllers," top domestic drive manufacturers secured entry tickets, but their profit models were forced to completely rewrite.
DapuStor's experience most directly reflects this shift in procurement power. In the first three quarters of this year, DapuStor recorded CNY 9.8 billion in revenue, over half from overseas, successfully entering Google and xAI data centers. However, behind this scorecard lies a passive factor: over 90% of NAND flash particles for exported standard drives must be purchased from Japan's Kioxia. When upstream prices rose, its Q3 gross margin was squeezed from 33.9% to 25.6%. When pivoting to the domestic market, top local cloud vendors adopted a more thorough approach—to hedge against module price hikes, cloud giants stopped buying finished brand drives, instead procuring NAND flash particles directly from Samsung and SK Hynix, then commissioning DapuStor for firmware adaptation and white-label custom packaging (domestic OEM systems generally accept the model where cloud factories self-supply 70% of materials, whereas overseas assemblers like Dell and Supermicro largely refuse). Regarding the 512TB ultra-large QLC drive displayed by DapuStor at overseas exhibitions, continuous writing takes nearly 40 hours; currently, it serves more as a technical demonstration for cold archiving. Comparing domestic and international scenarios, the path forward is clear: independent drive manufacturers without proprietary wafer capacity will become increasingly passive relying on selling standard hardware for price spreads. Only by earning engineering service returns through firmware tuning and custom packaging can they maintain certainty.
Since the premium on standard whole drives has been eroded, what landscape emerges when breaking through deeper into system layers and controller chips? Union Memory and Alibaba's T-Head offer contrasting references. In September this year, Union Memory collaborated with Intel to launch a tiered solution offloading inference caches to SSDs. Tests showed significant convergence in first-token latency for long conversations, but it remains in customer proof-of-concept stages without generating independent software licensing revenue. The true role of this system solution is as leverage to unlock whitelist access to major clients' data centers, protecting its hardware base of enterprise drives, which has held the No. 1 position in China for four consecutive years (15.5% share). At the controller chip stage, which determines the upper limit of drive latency, the only entity that has achieved closed-loop scaling in data centers is the cloud vendor itself: T-Head's Zhenyue 510 controller isolated garbage collection jitter from the hardware bottom layer, accumulating shipments of over 500,000 units and reducing extreme storage latency in Alibaba Cloud by over 90%. However, due to concerns about horizontal competition, such self-developed chips are difficult to export at scale to external internet cloud giants. Third-party controller vendors like Maxio remain primarily focused on the PC market, still waiting outside the data center gate for verification.
IV. What New Opportunities Do CXL, MRDIMM, and Novel Memory Interconnects Bring?
Observing whole-drive manufacturers maneuvering between rising particle prices and cloud vendor white-labeling, shifting the gaze upward one step to memory interconnect chips reveals almost a different business ecosystem: here, no wafer inventory is carried, yet gross margins stand firmly near 70%. However, the sector must currently endure a waiting period characterized by "excellent long-term positioning but hindered short-term realization."
In this race, Montage Technology plays the role of "channel gatekeeper"—every time computing giants reshape memory forms, chipmakers controlling protocols and power interfaces collect another toll. After server memory prices surged multiplicatively, cloud vendors urgently sought to revitalize old DDR4 sticks removed from retired servers. By attaching Montage's CXL controller chips, old memory installed in new servers suffers near-zero performance loss, while total system memory expenditure drops immediately by 25%–40%. In July this year, after calculating ROI, Samsung, SK Hynix, and Micron successively abandoned self-developed CXL controllers, allowing Montage to seize approximately 70% of the global controller share in early adoption. An interesting scene occurred in the NVIDIA camp: to alleviate conventional memory shortages and reduce energy consumption by 20–30%, NVIDIA partnered with Micron to launch pluggable low-power memory small modules (SOCAMM2), adding one 1:1 matched independent voltage regulator chip in the second-generation specification. Since NVIDIA does not engage in such small power devices, Montage and Renesas quickly entered the field, and related products are now commercially deployed in Microsoft data center projects.
However, examining Montage's revenue ledger for the first three quarters of this year—CNY 5.414 billion—the traditional DDR5 interface chips still carry the main weight. The reason new stories have not yet translated into current large sums is twofold: domestically, private super-node memory pool solutions divert traffic from intelligent computing centers, so mass adoption of standard CXL awaits the rise of North American cloud vendors in 2027; secondly, it is stuck on an unexpected bucket short board—server CPU shortages. Currently, Intel's server CPU order fulfillment rate remains at only 60–70%, and the inability to source core processors directly drags down assembly and shipment by OEMs. Although Multi-Rank DIMMs (MRDIMM) raise the value of single interface chips from over ten dollars to USD 60–70, actual order shares are still below 5%. True volume growth must wait for the batch delivery of next-gen CPU platforms in Q2 next year.
V. Why Can't CXMT and YMTC Be Absent from This Competition?
Tracing down from whole-drive solutions and control chips, one inevitably reaches the fundamental question: Who holds the wafer particles that account for 70–80% of storage hardware costs? When overseas manufacturers fully divert capacity to secure HBM, CXMT and YMTC face a critical window to wedge themselves into the foundation of domestic cloud data centers, though the challenges they face differ.
CXMT fought a pragmatic asymmetric battle. While the market often watches when it can conquer top-tier HBM, CXMT has already secured about 25% of video memory share in leading domestic cloud vendors' self-developed compute chips via implicit cooperation with SMIC production lines using previous-generation HBM2E. However, on the HBM3 and HBM3E standards configured for next-gen flagship cards, the technical barriers of the three major overseas manufacturers are indeed difficult to overcome head-on in the short term. Yet the other side of the coin hides a larger vacuum: manufacturing equal capacity of HBM consumes 3 to 4 times the wafer area of ordinary memory. When overseas giants prioritize HBM causing conventional DDR5 supply exhaustion, CXMT did not linger on its weaknesses but invested its main capacity entirely into server main memory and CXL capacity foundations. It recorded CNY 269 billion in revenue in the first three quarters, with gross margins approaching 90%, and even next year's enterprise capacity was pre-locked by cloud giants with CNY 7 billion in advance payments.
YMTC, also a manufacturing foundation, is engaged in a structural gear-shift racing against cycles. Relying on hybrid bonding technology licensed inversely to Samsung, YMTC's flash technology has joined the global first tier, achieving CNY 47 billion in quarterly revenue and nearly 79% flash gross margin in Q1 this year. However, a historically high proportion of consumer-grade products has led to value erosion, ranking third globally in shipment volume but only fifth in sales revenue. Consequently, the company is aggressively attacking server enterprise drives, aiming to capture nearly 40% of the domestic share within two years. What forces YMTC to accelerate this switch is the chilling wind blowing in the terminal market: while cloud vendors still lock in future capacity, PC manufacturers have been pushed into stagnant sales due to price hikes or losses due to price cuts, driven by memory prices surging 80% in a year. By the end of Q3, consumer channel inventory digestion cycles exceeded 12 months, motherboard makers cut production plans by 30–40% early in the year, and some channel dealers even recycled old DDR3 particles to refurbish outdated motherboards to minimize assembly costs. Shrinking terminal installations quickly transmitted to supporting SSDs; by late October, consumer flash spot prices began declining weekly. Combined with Wuhan Phase III new production lines entering ramp-up next year, whether YMTC can steadily deliver new wafers to data center rooms before consumer price declines spread directly determines its profitability resilience for next year.
VI. Who Really Makes Money? Value Redistribution in China's Storage Supply Chain
As this industrial tour concludes, extending from new Silicon Valley architectures to local wafer fabs, opening the cash flow statements of this year's Q3 reports clarifies who is earning real gold and silver versus who enjoys only paper wealth under the tide of cyclical price hikes.
Amidst the same rare price hike cycle, the warmth and cold across the supply chain differ starkly. CXMT, holding scarce wafer capacity, recovered over CNY 250 billion in net operating cash inflow through full production and fast sales. Montage Technology, guarding the interconnect channel, steadily enjoyed nearly 69% gross margins thanks to its asset-light structure with zero particle inventory. On the other end, comprehensive module enterprises Longsys, BIWIN, and TWSC recorded a combined net profit of CNY 31.8 billion in their P&L statements for the first three quarters, yet accumulated high-value inventories totaling CNY 81.5 billion in warehouses, resulting in a net operating cash outflow of CNY 26 billion, with Q3 gross margins dropping by 13–16 percentage points simultaneously. More severely, the playbook that module manufacturers relied on for survival—"hoarding particles at troughs, selling standard products at peaks"—is facing a pull-out rug as cloud giants enter direct procurement to lock goods and commission professional drive makers for white-label manufacturing.
Thus, this storage upheaval ignited by Agents and unfolding beyond HBM ultimately converges into a clear business logic: The migration of AI state data to the host side has indeed opened an incremental market several times the size of video memory; however, at every checkpoint through which data flows, hyperscale cloud vendors are manually flattening intermediary margins lacking technical barriers. On the future table, only two types of Chinese companies can sediment industry trends into long-term returns: those like CXMT and YMTC, becoming the capacity foundation of cloud rooms with irreplaceable wafer capacity; or those like Montage Technology and top custom enterprise drive vendors, embedding themselves in unavoidable data channels of large AI systems through interconnect power chips, self-developed controllers, or deeply customized firmware.