On October 19, the 2026 RISC-V China Summit was held in Shenzhen. Chen Zhijian, Founder and CEO of domestic RISC-V chipmaker SpacemiT, officially unveiled the company's first server-grade RISC-V chip, the V100, at the summit. Integrating 46 RISC-V cores and supporting 8-channel DDR5 and 52 PCIe 5.0 lanes, this chip is hailed as the "first computing chip to fully comply with RISC-V server specifications." It marks SpacemiT's official transition from the edge to the cloud, and signifies that RISC-V server chips now possess the delivery capability for "direct installation, booting, and running of general-purpose distributions."
Opening his speech, Chen Zhijian outlined the value migration path of the open-source ecosystem. He pointed out that during the PC and mobile internet eras, the information infrastructure of human society was built on open-source software such as Linux, MySQL, Android, and WebKit. As we enter the intelligent era, the scope of open source is expanding from software to large models, and further penetrating into the hardware domain. "Open-source hardware, open-source software, and open-source large models will constitute the three core elements of next-generation application innovation."
In his view, the core driving force behind the transformation of computing paradigms is shifting from Moore's Law to AI large models. Traditional devices are tools that passively execute precise instructions, whereas large models will endow devices with "intelligence," enabling them to proactively understand human intentions and provide services. This shift will give rise to new "species" such as digital employees, digital family members, and physical AI robots, driving a market scale expansion of more than tenfold. "In the future, population statistics will be calculated as the physical population plus the digital population."
Chen Zhijian believes that the rise of each generation of instruction set architecture does not replace legacy applications in the existing market, but rather pioneers applications on a tenfold scale in new markets. The intelligent computing era presents a "once-in-a-millennium opportunity" for RISC-V.
Three Chips in Three Years: Homogeneous Architecture Across All Scenarios
Chen Zhijian summarized SpacemiT's product R&D roadmap as "homogeneous architecture across all scenarios, homogeneous architecture across all domains, and one architecture with one codebase."
Homogeneous architecture across all scenarios means that chips for the endpoint, edge, and cloud are all built on RISC-V; homogeneous architecture across all domains means that the CPU computing power, AI computing power, and real-time control computing power within a single chip are all based on RISC-V. The core objective is to avoid the redundant consumption of engineering resources on x86 and Arm. "We hope RISC-V will be the ultimate destination of the future, allowing the entire human society to share the knowledge achievements of engineers," Chen Zhijian said.
Under this vision, SpacemiT maintains a pace of releasing a new generation of chips every year: in 2024, it launched the K1, the first mass-produced RVA22 Profile chip; in 2025, it launched the K3, the first mass-produced RVA23 Profile chip, supporting RVV 1024-bit vector width and native FP8 inference; and this year, it launched the latest V100, the first server-grade chip in its cloud product line.
V100: 46-Core Hybrid Architecture, Debuting XiangShan "Kunming Lake"
According to SpacemiT, the V100 chip integrates six high-performance RISC-V cores of XiangShan Kunming Lake V2R2 from OpenXLab and 40 high-efficiency RISC-V cores of SpacemiT's self-developed X100, bringing the total to 46 cores on a single chip. It can also be scaled up to 92 cores via dual-socket coherent interconnect.
Previous data shows that the "Kunming Lake" core is designed on a 7nm process, with a clock frequency reaching 3GHz and a SPECINT2006 score of 15 points/GHz. Its performance is comparable to the Arm Neoverse N2 core, and it can be widely applied in high-end chip fields such as server chips, AI chips, GPUs, and DPUs.
Chen Zhijian stated that the V100 is the first commercial CPU chip to integrate the XiangShan "Kunming Lake" (V2R2) processor core.
In terms of memory support, the V100 supports 8-channel DDR5 4800MT/s with a bandwidth of 307GB/s and a maximum capacity of 2TB per socket. For I/O, it provides 52 PCIe 5.0 lanes, supporting the deployment of 8-card AI acceleration.
Chen Zhijian emphasized that the V100 covers the five core components of the RISC-V server specifications: RVA23 Profile, Server SoC specification, Server Platform specification, Boot and Runtime Services (BRS) specification, and Security Model specification. Notably, passing all BRS specification tests means that mainstream Linux distributions such as openEuler, openKylin, Ubuntu, Debian, Fedora, Red Hat, and Rocky can be directly installed and booted without the need to customize an operating system for each individual chip.
In terms of virtualization, the V100 achieves full hardware support for Hypervisor 1.0, the AIA interrupt controller, and IOMMU, and its virtualization extensions have received native support from the upstream Linux community.
"The V100 project was initiated in 2023 and took three years to complete. At the hardware level, it involves seven subsystems, with a large number of core IPs being self-developed," Chen Zhijian stated. "The entire RISC-V specifications are also in the process of ratification. We track the specifications in real time and conduct IP R&D concurrently."
Agent Security: Replacing Containers with Lightweight Virtual Machine Sandboxes
During his speech, Chen Zhijian also specifically discussed the new requirements that Agent workloads pose to cloud CPUs. He pointed out that personal Agent applications such as Muse and Dots are emerging. These workloads are characterized by short lifecycles, untrustworthiness, machine execution, and ultra-large-scale concurrency. The current mainstream approach is to use containers to isolate Agents, but containers only provide process-level isolation. Once an Agent escapes, it may attack the host Linux kernel, thereby affecting the services of other Agents on the same machine.
"What Agents truly need is a computer of their own," Chen Zhijian revealed. SpacemiT, in collaboration with partners, has jointly developed a lightweight virtual machine sandbox solution based on the hardware isolation capabilities of the V100. The chip hardware provides the isolation structure, on which the KBM software layer runs, and above which lightweight virtual machines are hosted. This solution achieves VM-level security isolation while keeping resource overhead close to that of containers—when an Agent escapes, the affected scope is confined within the sandbox, without impacting the kernel or other Agents.
Three Types of Complete Machine Solutions Launched Simultaneously
Launched simultaneously with the V100 are three server complete machines: the C2201 computing server, the G5201 intelligent computing server, and the S5236 storage server. The G5201 supports eight double-width accelerator cards, has validated domestic accelerator cards such as Kunlunxin M100, supports high-speed RDMA cluster networking, and can run models like DeepSeek-V4.1-Flash. Chen Zhijian stated that the supporting motherboards, firmware, BMC management, and hardware reference designs can help partners reduce the workload of starting board-level development from scratch.
In his concluding remarks, Chen Zhijian candidly admitted that chip platform software optimization and developer operations require "massive investment, long cycles, and particularly low commercial returns," but SpacemiT will continue to pursue them. "The love and recognition from global developers are the driving force for our progress."
Editor: Chipwise - Langkejian