Author: He Luheng, Editor: Li Motian
In February 2024, the Select Committee of the U.S. House of Representatives released a venture capital review report [1], explicitly criticizing two U.S. venture capital firms for funneling funds to Chinese companies. One of the invested companies is SJ Semiconductor.
SJ Semiconductor is not widely known outside the industry, but its two founding backers are highly prominent. One is SMIC (Semiconductor Manufacturing International Corporation), the leading chipmaker in mainland China, and the other is JCET (Jiangsu Changjiang Electronics Technology), a major chip packaging and testing company.
In 2016, the two parties established a joint venture, SJ Semiconductor, targeting the final piece of the puzzle between chip manufacturing and packaging: Advanced Packaging.
In April this year, SJ Semiconductor was listed on the STAR Market, becoming the largest IPO on the A-share market in the first half of the year. On its first day of listing, its market capitalization exceeded 100 billion RMB, and three months later, it surpassed 350 billion RMB, rapidly breaking into the top 10 of the semiconductor sector.
China's industrial sector has high expectations for SJ Semiconductor, while the U.S. views it as a fish that slipped through the net of its strict containment. Four months after the release of the review report, the U.S. issued an official document, for the first time listing "advanced packaging technology and equipment" as the highest-level restricted zone prohibiting U.S. capital investment.
But the Americans know better than anyone else that this ban came a bit too late.
The Choke Point: Silicon Interposers
SJ Semiconductor has become a thorn in the side of the Americans because it has overcome another bottleneck in mainland China's chip manufacturing—the silicon interposer.
Advanced Packaging is a technology popularized by AI chips, and the silicon interposer is one of the key underlying technologies for advanced packaging. TSMC's (Taiwan Semiconductor Manufacturing Company) renowned CoWoS technology involves placing GPUs/CPUs and HBM (High Bandwidth Memory) on a silicon interposer, achieving high-speed connections by drilling and routing on it.
Expanding further, a single silicon interposer can accommodate more chiplets with different process nodes and functions, forming a highly powerful large chip. Compared to simply making the chip larger at the cost of low yield, this Lego-like assembly solution is clearly more cost-effective.
The essence of a silicon interposer is a silicon wafer substrate, which is not much different from the silicon wafers used to make chips, but its manufacturing difficulty is quite high.
Due to the addition of many extremely precise micro-processes such as drilling and routing, although it is called "packaging" technology, the processes, equipment, and materials used are not much different from chip manufacturing, which is beyond the capability of ordinary packaging and testing factories.
For a long time, only three companies in the world have been able to mass-produce silicon interposers at scale—TSMC, Samsung, and Intel, which happen to be the top three giants leading the way in chip manufacturing technology.
The difficulty of mass-producing silicon interposers can be seen from this.
Apple adopted TSMC's InFO technology as early as 2016, which can be understood as a lite version of CoWoS. What truly made the silicon interposer and CoWoS technology shine was NVIDIA's A100 released in 2020.
For China's chip industry at that time, the emergence of the silicon interposer path brought equal opportunities and risks.
Around 2020, it was a time of extreme alert and tension for China's IC (Integrated Circuit) industry. The disruption of the entire supply chain, from equipment and materials to EDA (Electronic Design Automation) software, made catching up in advanced process nodes an almost impossible task for China.
However, advanced packaging can largely bypass advanced process nodes to manufacture high-performance chips. The risk lies in the fact that if the development of advanced packaging technologies represented by silicon interposers is not accelerated, it will drag down the entire industrial chain, further widen the gap, and even cause China to fall behind again in the upcoming AI chip era.
Almost everyone who understands the underlying reality of China's chip industry has turned its attention to SMIC, hoping it can become the fourth chip manufacturing company to mass-produce silicon interposers at scale after the three giants.
But at this time, SMIC was already stretched thin. 2020 marked the beginning of a radical leap in SMIC's capital expenditures, most of which were invested in advanced process nodes.
In the middle of that year, SMIC was listed on the STAR Market, raising 53.2 billion RMB. However, the funds were mainly used for the establishment of advanced process production lines and R&D reserves. In the over-200-page prospectus, "advanced packaging" was not mentioned even once [2].
Objectively speaking, as one of the main targets of U.S. sanctions, it is understandable that SMIC took advantage of the window period when its existing equipment was still usable and technical support was still available, to concentrate its efforts on prioritizing the development of advanced process nodes and completing the process before policies were further tightened.
The capital expenditures directed towards advanced process nodes also put pressure on SMIC's gross profit margin, which dropped to 18% by the fourth quarter, while TSMC's gross profit margin reached as high as 53% during the same period.
Under such circumstances, taking on the burden of developing and mass-producing silicon interposers and advanced packaging would indeed be asking too much.
Thus, this extremely arduous task fell on the shoulders of SMIC's "own son"—SJ Semiconductor.
"The First Stock of Advanced Packaging"
Since its inception, SJ Semiconductor has taken on the crucial mission of "completing the supply chain."
Around 2014, the demand for high-end CPU/GPU/AI chips at home and abroad surged.
The packaging of such chips requires extremely high precision in bumping. Although mainland China has packaging and testing capacity, it severely lacks high-end technological reserves.
Not only did chips designed and manufactured domestically need to be sent overseas for packaging, but even wafers manufactured by foundries like SMIC for their clients had to be sent overseas for packaging and testing before being shipped back, bringing additional time and logistics costs.
This made SMIC realize the absence of domestic chip supply chains in advanced packaging, creating an urgent need to fill this gap.
Therefore, SMIC and its downstream partner JCET jointly established SMIC-JD in August 2014, which is the predecessor of SJ Semiconductor.
The purpose of the company's establishment was to fill the technological gap in the middle-end manufacturing of 12-inch wafers (including bumping, wafer-level packaging, etc.) in the domestic supply chain.
On SMIC's side, besides providing capital, they also provided personnel.
Cui Dong, who served as the Chairman and CEO of SMIC-JD, previously held the positions of Senior Vice President and Executive Vice President at SMIC. Along with Shen Yuehai, former Senior Manager of Testing at SMIC, Xue Xingtao, former Senior Manager of the Engineering Department at Wafer Fab 1 (Middle-End), and Tong Daming from the Process Integration Department, they together formed the initial technical team of SMIC-JD.
Cui Dong also poached two packaging heavyweights. One is Li Jianwen, a well-known packaging expert in the industry, who has worked at China Aerospace Science and Industry Corporation, Chartered Semiconductor in Singapore, Shanghai Hua Hong NEC, and Amkor Technology. During his time at Shanghai Hua Hong NEC, he participated in the construction of manufacturing production lines and later accumulated mass production experience in advanced packaging at Amkor, the world's second-largest packaging and testing company.
The other, Lin Cheng-chung, is relatively mysterious. The outside world only knows that he served as Deputy General Manager of the R&D Department at Nanya Technology, a major DRAM manufacturer in Taiwan, in the 1990s. From 1999 until joining SMIC-JD, he worked at TSMC, reaching the position of Technical Manager in the R&D Department, with specific business responsibilities unknown.
It is widely believed externally that he played a key role in building the technical system of SMIC-JD.
On JCET's side, it mainly assisted in undertaking supporting businesses for overseas advanced process chips. SMIC, SMIC-JD, and JCET joined hands to establish a complete chain of "front-end manufacturing - middle-end advanced packaging - back-end packaging and testing."
Besides its two "good fathers," another key figure in the early development of SJ Semiconductor was Qualcomm, a good friend of the Chinese people.
Qualcomm was originally a major client of SMIC. In 2015, when SMIC-JD introduced third-party capital, besides the National Integrated Circuit Industry Investment Fund (Big Fund), the other was Qualcomm Ventures.
In 2016, SMIC, SMIC-JD, and Qualcomm jointly announced the mass production of 14nm wafer bumping technology. It was precisely because of this investment that Qualcomm was explicitly criticized by the U.S. House of Representatives for being unpatriotic.
After successively overcoming advanced packaging challenges such as Wafer-Level Chip Scale Packaging (WLCSP) and high-density micro-bumps, in 2020, SJ Semiconductor completed the construction of its 2.5D technology platform based on silicon interposers, becoming one of the earliest domestic packaging companies to successfully develop silicon interposer technology.
At the end of that same year, SMIC-JD, along with SMIC, was added to the U.S. "Entity List." In April of the following year, SMIC transferred all its shares in SMIC-JD, and JCET subsequently withdrew from the list of shareholders.
In the same month, SMIC-JD was renamed SJ Semiconductor, becoming an independent advanced packaging company with no actual controller. It opened up investment channels to the outside world, and the scarcity of its technology made it a target for capital pursuit.
From 2021 to 2024, SJ Semiconductor seamlessly completed multiple rounds of financing, introducing local state-owned industrial funds such as various Wuxi Industrial Development Funds, as well as domestic top broker-affiliated funds (such as CMB International and CICC) and well-known PE/VC firms (such as Puhua and Jinpu) [3].
Walden International, another U.S. venture capital firm explicitly criticized by the U.S. House of Representatives, even braved the wind to invest $35 million in SJ Semiconductor a year after it was added to the "Entity List" (October 2021) [1].
In 2023, SJ Semiconductor's SmartPoser-Si platform achieved mass production, making it one of the earliest and largest-scale enterprises in mainland China for the mass production of silicon interposer 2.5D packaging technology platforms.
In October 2025, SJ Semiconductor's application for an IPO on the STAR Market was accepted. It wrote in its prospectus: [3]
"The SmartPoser-Si platform represents the most advanced level in this technological field in mainland China, and there is no technological generation gap compared to the world's leading enterprises."
Increasingly Larger Chips
While SJ Semiconductor is growing, AI chips are also running further down the path of becoming larger.
This "larger" is in a physical sense. NVIDIA's latest generation Blackwell B200 is a giant chip:
Two GPU main chips put together have an area of up to 1600mm², surrounded by 8 HBM3e chips, each occupying an area of 80-100mm².
These dies are placed on a silicon interposer, resulting in an unprecedented silicon interposer area of 2800mm², which is 1.65 times larger than the previous generation H100 (1 GPU + 6 HBM3s). TSMC had to employ its highest-specification CoWoS-L technology.
But the benefits are also tangible. With only a minor upgrade in the process node (4N->4NP), the AI large model training performance of the B200 is 2.5 to 4 times higher than that of the H100, the AI large model inference performance is improved by 15 times, and the energy consumption per token is only 1/25 of that of the H100.
The benefits of becoming larger are obvious, and competitors naturally do not want to fall behind NVIDIA.
Its old rival AMD's MI250X launched in 2021 used a silicon interposer area of 2,300-2,500mm², and the MI300X released in 2023 further increased it to 2800mm². Google's TPU iteration can also be called a "history of silicon interposers getting larger," evolving from 1000mm² for v2 in 2017 to 2800–3500+mm² for the latest 7x/8t.
The downside is that the larger chips have further squeezed TSMC's already limited CoWoS and silicon interposer capacity.
At the beginning of this year, industry insiders revealed that TSMC's current 1.15 million wafer CoWoS capacity has been completely divided among major giants, with NVIDIA taking 60%, AMD grabbing 8%, and the rest contracted by Broadcom and MediaTek (undertaking orders from Google, Meta, and OpenAI) [4].
At the annual general meeting of shareholders in June, TSMC stated that it is accelerating the increase of CoWoS capacity, which has already doubled compared to last year this year, and will double again next year.
However, whether this capacity expansion speed can keep up with the growth rate of demand remains to be seen. In the same month, Nomura Securities released a report stating that NVIDIA's demand for CoWoS has already surged by 50% compared to the estimates at the beginning of the year [5].
Jensen Huang publicly stated last year that there is currently no alternative to CoWoS [6]. The long-term supply shortage of AI chips is largely due to the insufficient CoWoS capacity, which has choked the main artery of the entire computing infrastructure construction.
However, the CoWoS choke point is an opportunity for mainland China to make up for its disadvantages.
On the one hand, the barefoot are not afraid of those who wear shoes. As early as the beginning of 2025, the U.S. used new bans to cut off the path for Chinese chip companies to adopt TSMC's CoWoS. The severe shortage of CoWoS capacity has instead forced most Western companies that cannot get capacity onto the same starting line as Chinese enterprises, which is what is meant by "as one rises, the other falls."
On the other hand, the existence of SJ Semiconductor provides domestic chip companies with an additional fallback option.
According to SJ Semiconductor's prospectus, the proportion of its domestic sales revenue in its main business has increased from 79.77% in 2022 to 93.86% in 2025, and its top five clients include "leading domestic AI high-computing chip enterprises" [3].
Regarding the several AI chips recently released by well-known domestic manufacturers, industry insiders revealed that they use SJ Semiconductor's 2.5D packaging.
Simply in terms of technical level, regarding the silicon interposer size, which is one of the core indicators, SJ Semiconductor has achieved a maximum size of about 3 times the reticle size. For comparison, TSMC currently only achieves 3.3 times the reticle size.
Although Samsung can also achieve a 3-times reticle size, it lags behind SJ Semiconductor by a step in another core indicator, the "minimum micro-bump pitch" (40um vs 20um) [3].
Looking at the domestic packaging and testing industrial chain, SJ Semiconductor has made up for the shortest plank in the chain, complementing the advanced packaging technologies of other domestic packaging and testing giants.
The 2.5D/3D packaging (XDFOI platform) developed by JCET replaces the silicon interposer with an organic RDL stacked interposer. Although it sacrifices connection density, both the material itself and the manufacturing process are much cheaper than manufacturing silicon interposers, making it a highly cost-effective alternative.
TFME (Tongfu Microelectronics) excels in system-level assembly and testing after chip dicing (such as large-size FCBGA and Chiplet), which perfectly complements silicon interposer technology. SJ Semiconductor is responsible for assembling the chips on the silicon base, while TFME is responsible for assembling and testing the entire system, which is equivalent to establishing a complete packaging process similar to TSMC's CoWoS.
Hua Tian Technology's specialty lies in automotive-grade chip and memory packaging.
Each of the major giants has its own strengths, making mainland China's advanced packaging arsenal unprecedentedly abundant.
In 2025, in the global OSAT (Outsourced Semiconductor Assembly and Test) revenue ranking, five mainland China manufacturers squeezed into the top ten, with a combined market share reaching 32.6% [7]. The highest-ranked JCET and TFME both hit record-high revenues, with advanced packaging revenue accounting for over 70% [8].
Next, what SJ Semiconductor and the older giants need to do, besides further bridging the technological gap with TSMC, is to expand production, and expand it again.
Epilogue
The chip industry in mainland China had a difficult start, missing the technological progress cycle of the 1980s and 1990s, and since then, the technological gap with the West has been calculated in generations.
The packaging and testing segment was the earliest to catch up with international levels. Starting with JCET entering the global top 10 packaging and testing companies for the first time in 2009, it began to compete on the same stage with international first-tier giants. Subsequently, a group of domestic peers such as TFME rose up, rapidly bridging the scale gap with international giants.
However, from a technical perspective, to be fair, over the past decade, mainland China's packaging and testing has always been in the context of being "one step behind." In some high-precision and cutting-edge fields, the gap with international giants has always been one step.
The collision of advanced packaging and generative AI has created a new starting line. The rivalry among major powers has fragmented the supply chain, but it has also exchanged greater market space for mainland China's packaging and testing companies, giving them the capital to compete with international giants once again, which has led to today's close pursuit.
In November 2024, the Center for Strategic and International Studies (CSIS) released a report titled "The Double-Edged Sword of Semiconductor Export Controls: Semiconductor Manufacturing Equipment," pointing out that advanced packaging is a typical field reflecting China's accelerated "design-out" of U.S. technology [9].
"In the field of advanced packaging, China is breaking away from the traditional 'fast-follower' model and shifting towards more innovative approaches. This represents a critical shift in U.S.-China technological competition and could potentially threaten the long-term innovation leadership of the United States [9]."
Many times, it is your opponents who know you best.
References
[1] How American Venture Capital Fuels the PRC Military and Human Rights Abuses, Select Committee of the U.S. House of Representatives;
[2] SMIC Prospectus
[3] SJ Semiconductor Prospectus
[4] One TSMC, 1.15 Million Wafers, and the "Chip War" in 2026, Wu Zihao
[5] Gap Reaching Up to 20%! TSMC Admits Advanced Packaging Capacity is Urgent, Some Orders Have Overflowed, Cailian Press
[6] NVIDIA CEO Jensen Huang Reaffirms Firm Cooperation with TSMC, Stating: The Cooperation Between the Two is Irreplaceable, Global Times
[7] 2025 Global OSAT Top 10 List, Mainland China Occupies Five Seats, XinSixiang Research Institute
[8] JCET and TFME 2025 Annual Reports
[9] The Double-Edged Sword of Semiconductor Export Controls: Semiconductor Manufacturing Equipment, Center for Strategic and International Studies