[Related Companies Mentioned in This Article] BOE, WG Tech (TGVTECH), Sky Semiconductor, Lens Technology, Rainbow Shares, Triumph Science & Technology, GobiJia, Qibin Group, Corning, SCHOTT, AGC, NEG, MKS Atotech, MacDermid Alpha, Dongwei Technology, Tiancheng Technology, Aisen Shares, Hwatsing Technology, DNP, JNTC, Yoke Technology, Nata Opto-electronic Material, Jiangfeng Electronics, Grinm Advanced Materials, Shanghai Sinyang, Anji Microelectronics, Zhongjuxin, Feikai Materials, Guanghua Technology, Soitec, National Silicon Industry Group (Xinao Technology), Guangdong Silifeng, Element Six, Coherent, Diamond Foundry, Sumitomo Electric, Akash Systems, Huahedianzi, Liliang Diamond, Huanghe Whirlwind, Central South Diamond, Sf Diamond, Guoji Precision, Worldde, etc.
I. Key Materials Map: Position of Seven Types of Materials in AI Accelerator Packaging
Every structural upgrade in advanced packaging is accompanied by a generational shift in materials. Figure 1 uses an "2.5D/3D+CPO" package for an AI accelerator as an example to mark the positions of seven key materials: ① TSV silicon interposer, ② TGV glass substrate, ③ Hybrid bonding dielectric SiO₂/SiCN, ④ High-purity electroplated copper electrodes, ⑤ Silicon photonics SOI wafers, ⑥ IOX ion-exchange glass waveguides, ⑦ Diamond heat spreader. From bottom to top, above the PCB mainboard is a glass-core substrate with ABF build-up layers, followed by the TSV silicon interposer, where GPU/ASIC and HBM stacks are placed side-by-side on the interposer; on the sides, EIC driver chips and PICs (SOI) form the optical engine, with optical paths routed from inside the glass core; the diamond heat spreader/lid at the very top handles thermal flows exceeding 1–2 kW.
The seven types of materials correspond to three performance main lines: interconnect density (① TSV/② TGV, ③ bonding dielectric, ④ electroplated copper), optical interconnect (⑤ SOI, ⑥ IOX waveguide), and heat dissipation (⑦ diamond heat spreader). Each material generation step results in a leap in interconnect pitch, bandwidth, or thermal design power. Figure 2 summarizes the positioning, key processes, and domestic representative companies for each type of material.
Domestic substitution shows a gradient distribution: TSV/TGV and electroplated copper have entered mass production and small-batch production; SiCN bonding dielectrics, SOI, and diamond heat spreaders are in validation and small-batch stages; IOX glass waveguides are still in R&D. The following sections elaborate on each.
II. Materials①②: TSV Silicon Interposer vs. TGV Glass Substrate—Performance Boundaries and Domestic Process Chains
Material ① TSV silicon interposer and Material ② TGV glass substrate are the two "electrical routing" bases in 2.5D/3D packaging. Table 1 compares silicon, glass, and organic (ABF/BT) interposer/core materials using typical industry values: Silicon wins in wiring density and thermal conductivity, capable of sub-micron front-end BEOL wiring and ~150 W/m·K thermal conductivity, but limited by 12-inch wafer size and cost; Glass wins in low loss, tunable CTE, and panel-level processing, with dielectric loss factor (Df) of only 0.001–0.003, tunable CTE of 3–8 ppm/K, and processability on 510×515 mm panels, but suffers from poor thermal conductivity (1.1–1.4 W/m·K) and brittleness; Organic materials offer the lowest cost and mainstream mass production, but wiring capability and CTE matching are approaching their limits.
The two will coexist long-term and be used in different scenarios: Silicon interposers remain the main force for ultra-high-density 2.5D interconnects (domestic representatives: XMC, SJ Semiconductor, Tiancheng Advanced Semiconductor, with processes including deep silicon etching, insulation liners, and copper filling); Glass targets next-generation large-size cores and interposers (domestic representatives: BOE, WG Tech, Sky Semiconductor, as well as raw sheet manufacturers like Rainbow Shares and Triumph Science & Technology).
TGV manufacturing can be broken down into a five-step process chain (Figure 3): ① Glass raw sheet → ② Laser modification + wet etching → ③ Seed layer PVD → ④ Through-hole plating → ⑤ Planarization + RDL. International and domestic suppliers for each stage are as follows:
▸ Glass raw sheet: International: Corning, SCHOTT, AGC, NEG; Domestic: Rainbow Shares, Triumph Science & Technology, GobiJia, Qibin Group.
▸ Laser modification + wet etching: International: LPKF (LIDE), Plan Optik; Domestic: DR Laser, Han's Laser, HGLASER, Delong Laser.
▸ Seed layer PVD: International: Applied Materials, etc.; Domestic: Naura Technology, Matrix Technology.
▸ Through-hole plating: International plating solutions: MKS Atotech, MacDermid Alpha; Domestic equipment: Dongwei Technology, ACM Research; Domestic plating solutions: Tiancheng Technology, Aisen Shares. Tiancheng Technology's TGV through-hole plating AR 10–15 metrics have surpassed international brands; JNTC has compressed copper fill time to the minute level.
▸ Planarization + RDL: Requires TTV < 0.5 μm, Ra < 0.3 nm; Domestic: Hwatsing Technology (CMP equipment), BOE, WG Tech (multi-layer RDL).
Judgment: The domestic TGV process chain exhibits the characteristic of "equipment leading, raw sheets lagging"—laser, plating, PVD, and CMP equipment all have domestic mass production orders, while high-end specialty glass raw sheets remain the biggest weakness.
III. Material③: Hybrid Bonding Dielectric Evolving from SiO₂ to SiCN
Hybrid Bonding is the true bumpless 3D interconnect technology, with typical applications such as TSMC SoIC and AMD3D V-Cache. Its interface consists of ultra-flat inorganic dielectrics (SiO₂ or SiCN) and high-purity electroplated copper electrodes: after room-temperature alignment, heating annealing achieves dielectric-dielectric covalent bonding and copper-copper metal grain boundary diffusion fusion, allowing interconnect pitches to shrink below 1 micron.
The process is divided into three steps: Surface preparation → Room-temperature pre-bonding → High-temperature annealing. Dielectrics first form hydrogen/covalent bonds at room temperature; during annealing, copper expands to close voids and interdiffuses. The dielectric surface thus determines the mechanical strength and reliability of the bond.
Currently, the mainstream dielectric is SiO₂, which supports mass production at ~1 μm pitch (CIS/3D NAND). As pitches enter the sub-micron range, SiCN becomes the evolution direction: Higher bonding energy after activation of Si–C/Si–N surfaces; High strength achieved at 250°C annealing without degradation at high temperatures; Acts as a copper diffusion barrier and passivation layer itself, also blocking gas diffusion; Better interface thermal stability, facilitating multiple subsequent processes. In terms of scalability, imec has advanced W2W pitch from 400 nm in 2023 to 200 nm in 2026.
Industry Chain and Domestic Progress: Internationally, Applied Materials launched the Insepra SiCN deposition system (claiming the highest dielectric bonding strength in the industry), while EVG and Besi lead in bonding equipment. Domestically, Piotech covers about 100 types of dielectric processes with PECVD/ALD; Dione 300 (W2W) has received repeat orders, Pleione (D2W) has been shipped, supported by Propus pretreatment and Crux/Ascella metrology; Regarding precursors, Yoke Technology, Nata Opto-electronic Material, etc., are promoting the domestic substitution of silicon-based precursors.
Judgment: SiO₂ already supports mass production at ~1 μm pitch; entering sub-micron pitches, SiCN becomes the mainstream evolution direction due to higher bonding energy, built-in copper barrier, and lower annealing temperature. The domestic path relies on "equipment + precursor" dual wheels: Piotech has connected deposition—activation—bonding—metrology; the next hurdle is SiCN low-temperature deposition, surface roughness, and precursor purity/batch consistency.
IV. Material ④: High-Purity Electroplated Copper Electrodes—From "Full Filling" to "Grain Control and Low-Temperature Bonding"
Why "High Purity + Fine Grain": Hybrid bonding relies on copper atoms diffusing across interfaces at low temperatures; impurities and coarse grains cause voids and increased contact resistance; fine-grained/nano-twinned copper can reduce Cu–Cu bonding temperature to below 200°C. Therefore, requirements for electroplated copper have upgraded from the TSV era's "full filling" to "grain control and low-temperature bonding." The manufacturing of hybrid bonding copper electrodes includes five procedures (Table 3).
Table 3: Five Procedures for Hybrid Bonding Copper Electrodes and Industry Chain. Source: "Analysis of Technological Innovation and Competitiveness of Advanced Packaging Plating Solution Manufacturers"; Public data from MacDermid Alpha, imec; Company announcements; Compiled by Shenxinmeng.
Compared with international leading levels (Table 4): International players have achieved fine-grained copper below 0.2 μm with controllable orientation; Domestic players are at 0.5–2 μm, with orientation control still in R&D; International players have established nt-Cu systems and <200°C low-temperature bonding; Domestic player Tiancheng Technology is developing special structure additives but has not yet reached mass production; In terms of plating solution purity, Aisen's high-purity copper sulfate base liquid has reached ppb level, but gaps remain in additives; For TSV through-hole filling, international standards are AR ≥15:1 and void rate <0.01%, while domestic standards are AR 10–15:1 and void rate < 0.1%.
Table 4: High-Purity Electroplated Copper: International Leading vs. Domestic Status. Source: "Analysis of Technological Innovation and Competitiveness of Advanced Packaging Plating Solution Manufacturers"; Public data from MacDermid Alpha, imec; Compiled by Shenxinmeng.
Looking at the 2025 market performance index of domestic electroplating solution manufacturers (Figure 6, based on a quantitative model of five dimensions: technology, finance, profitability, market, and capacity), Anji Microelectronics (358.16) and Shanghai Sinyang (258.6) lead, followed closely by Aisen Shares (181.8), Tiancheng Technology (179.61), Guanghua Technology (175.36), and Feikai Materials (169.38). Copper electroplating solutions account for approximately 65% of domestic advanced packaging coating materials.
Judgment: TSV/RDL copper electroplating solutions have achieved substitution capabilities; gaps are concentrated in ultra-fine-grained copper for hybrid bonding and additive purity; "Solution + Equipment + Process" collaborative verification is the key to breakthrough.
V. Materials ⑤⑥: Silicon Photonics SOI and IOX Glass Waveguides—Two "Baseboards" for CPO Optical Interconnect
Materials ⑤ and ⑥ are the two "baseboards" for CPO optical interconnect: SOI is the "on-chip optical path" (PIC manufacturing substrate), while IOX is the "in-substrate optical path" (the last millimeter from fiber to chip); the ramp-up of CPO will drive both simultaneously.
Material ⑤ Silicon Photonics SOI Wafer: Smart Cut bonded stripping manufacturing. The process involves four steps (Figure 7): ① Thermal oxidation to generate SiO₂ on the surface; ② H⁺ implantation to form a hydrogen-induced splitting plane; ③ Flip bonding to bond with the support wafer at room temperature; ④ Stripping + polishing to obtain ultra-thin uniform top silicon, with remaining pieces recyclable. From top to bottom, the finished product consists of 220 nm top silicon (n≈3.48), buried oxide SiO₂ (BOX, n≈1.44), and silicon handle. The high refractive index difference between top silicon and buried oxide confines light within sub-micron waveguides, making SOI the standard substrate for silicon photonics PICs.
In terms of landscape, Soitec holds Smart Cut patents and accounts for over 95% of the global share for silicon photonics SOI; Domestically, National Silicon Industry Group (Xinao Technology) is advancing, XMC's "Chip-Light Plan" focuses on optoelectronic integration—SOI, and Guangdong Silifeng also has deployments. Every PIC requires an SOI substrate, meaning CPO ramp-up implies rigid demand for silicon photonics SOI. Domestic silicon photonics SOI is in the validation and small-batch stage; top silicon thickness uniformity and low defect density are the thresholds for entering the optical module supply chain.
Material ⑥ IOX Ion-Exchange Glass Waveguide: Glass "routing light" itself. In an AgNO₃/NaNO₃ molten salt bath, Na⁺ in the specialty glass substrate is replaced by Ag⁺, locally increasing the refractive index by Δn≈0.01–0.02; Field-assisted diffusion then forms embedded graded-index waveguides (mask windows control waveguide position), with propagation loss of 0.041 dB/cm, enabling 250→50 μm fan-in and mode field transformation within the glass (Figure 8).
Measured data from Corning's GlassBridge demonstrates the mass production value of IOX waveguides (Table 5): Single-ended coupling loss of 1.44 dB, alignment tolerance relaxed by 30 times (±30 μm), single-channel assembly < 15 s, mass production yield > 90%, and optical engine BOM reduced by 20%–30%.
Table 5: Traditional FAU Active Alignment vs. Corning GlassBridge Measured Data. Source: Corning announcements and IEEE ECTC 2026; "Research Report on the Fusion Industry Chain of Glass Substrates and Silicon Photonics"; Compiled by Shenxinmeng.
Corning launched GlassBridge in 2026 (disclosed at ECTC 2026) and verified edge coupling of glass waveguides with GlobalFoundries; Core IOX processes such as ion-exchange furnaces and field-assisted diffusion are mastered by Corning, while domestic efforts are still in the R&D stage.
Judgment: These two types of materials represent the most prominent weaknesses in domestic substitution—silicon photonics SOI is highly monopolized by Soitec, and IOX glass formulas and processes are dominated by Corning; "Specialty glass raw sheets + SOI substrates" should be listed as priority areas for material breakthroughs.
VI. Material ⑦: Diamond Heat Spreader—Breaking the "Thermal Wall" for Kilowatt-Level AI Chips
GPU single-chip power consumption is rising rapidly: from 400 W for A100, 700 W for H100, 1000 W for B200, to 1200 W for Rubin, with Feynman expected to exceed 2000 W (Figure 9 left). 3D SoIC and 16-layer HBM4 make it difficult for heat to escape, turning heat dissipation into the second wall after interconnect. Diamond's thermal conductivity reaches 1800–2200 W/m·K, 4–5 times that of copper (401 W/m·K), with a CTE of ~1.1 ppm/K, close to silicon, making it a key material for breaking the thermal wall (Figure 9 right).
Diamond cooling has four technical routes (Figure 10): CVD diamond heat spreaders with thermal conductivity of 1800–2200 W/m·K, attached to the back of the chip or lid, already in mass production; Diamond-copper composites with thermal conductivity of 600–900 W/m·K, tunable CTE of 6–9 ppm/K, easy to process, in small-batch production; Direct diamond bonding integrates wafer-level D2W with the chip, removing TIM interface thermal resistance, still in R&D; Diamond-SiC composite cold plates are system-level liquid cooling solutions for >1 kW chips, in validation. International vendors include Element Six, Coherent, Diamond Foundry, Sumitomo Electric, Akash Systems; Domestic vendors include Huahedianzi, Liliang Diamond, Huanghe Whirlwind, Central South Diamond, Sf Diamond, Guoji Precision, Worldde.
Domestic Breakthrough: Sky Semiconductor + Xiamen University + Huawei. At ECTC 2026, Sky Semiconductor, jointly with Xiamen University and Huawei, demonstrated wafer-level diamond cooling bonding results (Figure 11): On a 4-inch polycrystalline diamond wafer, 65 silicon chips were integrated in one go via low-temperature collective D2W bonding; Plasma activation + metal nanolayers were used to reduce interface thermal resistance; Temporary bonding suppressed warpage, reducing it by 67%; Reliability tests including high-temperature storage, reflow, and thermal cycling were passed. Its significance lies in moving diamond from "patches" to wafer-level integration.
Judgment: China possesses scale advantages in synthetic diamond production capacity; Sky Semiconductor + Xiamen University + Huawei have cracked wafer-level bonding; The next focus is on large sizes above 8 inches, precision polishing, and interface thermal resistance.
VII. Summary and Outlook: Materials Are the Main Battlefield for the Next Stage
Viewing platforms and materials in the same domestic substitution matrix (Table 6). On the platform side, 2.5D silicon interposers, 3D microbumps, and memory W2W hybrid bonding are in mass production; Compute-in-memory 3D (Hubei Starlight Technology) is in risk production; D2W, glass cores, and CPO are in validation—domestic advanced packaging has moved from "can we do it" to "yield, cost, and customer adoption." On the material side, overall progress lags behind platforms by about one step: TSV/RDL copper electroplating solutions lead in mass production; Silicon photonics SOI and diamond heat spreaders are in small batches; SiCN bonding dielectrics and specialty glass raw sheets are in validation; Fine-grained/nano-twinned copper and IOX glass waveguides are still in R&D.
Table 6: Domestic Substitution Phase Matrix: Platforms have landed in batch production, materials are in the "validation → scaling up" ramp-up period. Source: Company announcements, prospectuses, and semi-annual reports; Industry research and exhibition data; Phase judgments are evaluations by Shenxinmeng based on public information, as of October 2026.
Table 7: Outlook for Key Milestones in 2026–2030 (Including Expectations). Source: Previous sections; Yole; Company announcements; Time nodes include public plans and Shenxinmeng expectations, for reference only.
Materials are the main battlefield for the next stage. Based on the review of seven types of materials, we provide three judgments:
Judgment 1 | Materials: Moving from "Single-Point Substitution" to "System Synergy." Electroplating solutions, bonding dielectrics, SOI, specialty glass, and diamond must undergo joint verification with equipment and processes; The winning factors for domestic materials lie in purity, batch consistency, and packaging factory certification cycles. Keywords: Purity · Consistency · Joint Verification.
Judgment 2 | Platforms: 2.5D/3D Entering "Mass Production + Ramp-Up." SJ Semiconductor's 2.5D revenue exceeds half, and XMC's wafer-level 3D is in mass production; The next step is yield ramp-up and customer adoption for 3.3x reticle interposers, silicon bridges, and D2W hybrid bonding, which will directly determine the volume pace of materials like TSV, SiCN, and electroplated copper. Keywords: Yield · Capacity · Customer Adoption.
Judgment 3 | Frontier: Triple Fusion of Glass + Light + Heat. Glass core boards simultaneously carry TGV electrical routing and IOX optical routing, while diamond breaks the kilowatt-level thermal wall; Around 2028, a new generation of AI packaging paradigm featuring "Glass-Based CPO + Diamond Cooling" is expected to emerge. Keywords: Glass-Based CPO · Diamond Cooling.
References:
[1] imec. (2023). Wafer-to-wafer hybrid bonding: pushing the boundaries to 400 nm interconnect pitch. IEDM 2023.[2] imec, EVG. (2026). Cu/SiCN wafer-to-wafer hybrid bonding at 200 nm pitch.[3] Semiconductor Engineering. (2026-07). Alternative Materials for Hybrid Bonding.[4] Domestic Advanced Packaging & Key Materials: Frontier Technology Highlights and Industrial Outlook - ppt - Lu Bing, China Semiconductor Industry Insight Forum. (2026-10-16).