As AI shifts from training to inference and Agentic AI, KV cache, long context, and large-scale data lakes are shifting the pressure from the compute side to the memory and storage side. Relying solely on HBM (High Bandwidth Memory) to stack bandwidth is no longer sufficient; systems need to re-tier across bandwidth, capacity, latency, and energy efficiency. At the recently concluded OCP 2026 Global Summit, the latest showcases from Samsung, SK hynix, Marvell, and DapuStor perfectly outline this new trend.
01. Barometer: Is the Storage Narrative at OCP 2026 Being Rewritten?
The OCP 2026 Global Summit acts as a mirror, reflecting the storage anxiety of AI infrastructure and the response paths of vendors.
Samsung brought HBM5 and HBM4E concept models and wafers to the event, and jointly demonstrated CXL memory pooling with AMD; SK hynix pushed "memory-centric" to the system level with CMM-DDR5, MARS rack-level memory systems, and HBF (High Bandwidth Flash); Marvell released its second-generation Structera X CXL memory expansion controller while showcasing its 102.4Tbps switch chip and optical interconnects on the booth; DapuStor pushed single-drive capacity to new heights with its 512TB QLC SSD.
The industry believes that these highlights, seemingly scattered, actually point to the same issue: AI clusters no longer need just a faster memory chip or a larger SSD, but a tiered storage architecture that can organize HBM, CXL memory, flash memory, and interconnects.
For this very reason, the new signal released by OCP 2026 is not the refresh of a single parameter, but the evolution of storage from an ancillary device within servers to a system-level architectural variable. Moving forward along collaborative technologies such as memory, flash, and CXL, this main thread will become clearer.
02. HBM Guards Bandwidth, HBF Supplements "Capacity"
At the top of the AI memory pyramid, HBM remains the unavoidable answer. At OCP 2026, Samsung showcased concept models and wafers of its eighth-generation HBM5 and seventh-generation HBM4E, and launched customized HBM solutions tailored to the differentiated bandwidth and capacity requirements of various AI accelerators.
SK hynix, on the other hand, exhibited mainstream products such as HBM4 and HBM4E, continuing to consolidate its presence in AI memory. These moves indicate that HBM competition has shifted from merely pursuing generational leadership to customization and system adaptation centered around AI accelerators.
However, despite its high bandwidth, HBM has limited capacity, making it impossible to fit all KV cache and long context in AI inference into HBM. Thus, HBF (High Bandwidth Flash) was introduced.
The technology roadmap released by SK hynix shows that HBF is positioned as a capacity supplement to HBM, with a bandwidth about half that of HBM but a capacity far exceeding it. The goal is to provide a high-capacity storage layer with near-HBM bandwidth for warm data, supporting a hot-warm-cold data tiering architecture.
In other words, HBM continues to guard the bandwidth tier, while HBF supplements the capacity tier, and the memory system begins to extend from a single DRAM to multi-tier media. This approach also explains why both Samsung and SK hynix are emphasizing system-level reconstruction rather than just talking about the speed of a single memory chip. Changes in the memory tier will inevitably pass the pressure down to the flash tier.
03. Behind the 512TB SSD: Flash Memory is Becoming the Capacity Foundation for AI
As capacity pressure moves down, SSDs are no longer just cold data repositories, but have become the capacity foundation in AI data tiering.
The 512TB QLC SSD showcased by DapuStor at OCP 2026 is the most intuitive footnote to this trend. Previously unveiled at FMS 2026, this product doubles the capacity of the 245TB solution, providing 1PB of flash capacity with just two drives, targeting large-scale AI datasets, data lakes, and capacity-intensive infrastructure.
In laboratory tests, its 128K sequential read performance reaches 10.3GB/s, 128K random read bandwidth is 4.02GB/s, and 4K random read performance is 1.756M IOPS. These figures demonstrate that the increase in single-drive capacity is not merely about stacking capacity, but about reducing the number of SSDs and improving storage density in PB-scale deployments while maintaining performance.
Samsung's booth supplemented another perspective from the angle of system synergy: next-generation enterprise SSDs, KV cache optimization technologies, and the collaboration of CXL memory with high-density QLC SSDs for cache offloading, building a multi-tier storage system from HBM to SSDs.
The PCIe 6.0 SSD controller exhibited by Marvell paves the way for next-generation SSDs from the controller and interconnect sides.
It can be seen that competition in the flash tier is shifting from "larger capacity" to a combined optimization of "capacity density, performance, latency, and thermal management." DapuStor also showcased liquid-cooled enterprise SSDs and ultra-low latency SCM (Storage Class Memory), covering the needs of different AI workloads.
After SSDs thicken the capacity foundation, a new problem arises: how can this capacity and memory be efficiently shared across clusters, rather than being trapped in individual servers?
04. CXL and Interconnects: Making Tiered Storage Truly "Flow"
This is exactly why technologies such as CXL made intensive appearances at OCP 2026. Samsung and AMD jointly demonstrated a CXL-based CMM-D memory pooling solution, enabling dynamic sharing of memory resources among multiple servers to directly address the memory pressure caused by the rapid growth of KV cache in AI inference.
SK hynix released its second-generation CMM-DDR5 memory module with a capacity of 256GB. Based on the CXL 3.2 standard, its bandwidth is increased to 80GB/s, doubling that of the previous generation, with energy efficiency optimized by about 30%, and it supports CXL Pooled functionality. Its MARS rack-level memory system goes a step further by decoupling memory from servers to build a rack-level shared memory pool, supporting zero-copy data sharing between CPUs and GPUs. In Agentic AI scenarios, it jointly demonstrated with AMD and Marvell the sharing of KV cache through pooled memory to reduce inference latency.
Marvell's second-generation Structera X series CXL memory expansion chips, the 3406 and 3506, support six-channel CXL 3.2 interfaces for the first time, increasing the number of channels by 50% compared to the previous generation. They can connect up to 9TB of DDR4 or 6TB of DDR5 memory, support multi-host sharing, and feature built-in LZ4 compression. Officially, it is claimed that they can increase memory utilization by 2 to 3 times and reduce the first-token latency in AI inference by 40% to 50%. The products have been demonstrated on-site at OCP and are expected to begin sampling in the first quarter of 2027.
Besides CXL, near-memory computing is also reducing data movement. Samsung's LPDDR5X-PIM performs computations inside the memory chip, while SK hynix's CMM-Ax integrates some computing functions into the memory module, targeting scenarios such as long-context LLM services. Moving further up, pooling and tiering are also inseparable from high-speed interconnects and switching.
Marvell's Teralynx T100 single-chip 100Tbps Ethernet switch chip supports up to 102.4Tbps full-duplex line-rate throughput and integrates 512 200G SerDes lanes. It was jointly showcased with CyberTAN to present the blueprint for the Pallas series liquid-cooled switches based on this chip. Adopting direct-to-chip liquid cooling, it can manage over 1000W of thermal power dissipation with a PUE as low as 1.1. Its 1.6T DSP, 800G ZR/ZR+ coherent optical modules, and active cable solutions enhance high-speed interconnect capabilities across data centers and within racks. Security and ecosystems were not absent either; Marvell, together with Microsoft and Oracle, established the OCP Hardware Security Workgroup to promote the standardization of integrated HSMs. The 2nm GAA wafers, Groq LPU wafers, and NVIDIA Groq 3 LPX systems exhibited by Samsung reflect deep participation in advanced process foundry and the AI chip ecosystem.
Putting these developments together, the new trend at OCP 2026 is quite clear: HBM continues to break through bandwidth limits upwards, HBF and QLC SSDs thicken the capacity tier, CXL and rack-level memory pooling make memory resources flow, while switching, optical interconnects, liquid cooling, and security standards provide the foundation for system synergy. The competition among storage vendors is shifting from single-device parameters to the capability of system-level solutions.
For more memory market dynamics, technology evolution, supply and demand changes, and price trends, you are welcome to register for the MTS2027 Storage Industry Trend Seminar hosted by TrendForce on December 8.