As generative AI large models and massive data computing experience explosive growth, the deployment of global AI servers is expanding at an exponential rate. However, behind this computing boom lies an unprecedented "gray rhino" crisis of power consumption and thermal management.
According to estimates by the IEA and Yole Group, under the most severe scenario, by 2030, the annual power consumption of global data centers will surge to 2,000 TWh, quadrupling current levels, and even surpassing the total electricity consumption of traditional heavy industries such as aluminum, steel, and cement. In a single AI server rack, the total hardware power consumption is skyrocketing from the traditional 10-20 kW to a historical limit of 600 kW or even 1 MW. Meanwhile, the thermal design power (TDP) of a single AI chip is gradually breaking through the kilowatt level, heading towards 2,000 W to 3,000 W.
Source: IEA, Yole Group, Murata
As chip power increases significantly while the available mounting area on the motherboard remains fixed, the traditional hardware design architecture is no longer sustainable.
Murata Manufacturing Co., Ltd. (hereinafter referred to as Murata), a global leader in passive components, pointed out in a recent media interview: "Next-generation power management and efficient optical transmission are critical to achieving higher-level AI computing." Murata is comprehensively disrupting and reconstructing the power delivery network (PDN) and high-speed optical module designs for data centers through material and process innovations focused on "miniaturization" and "high density."
The Power Delivery Network (PDN) is Shifting from 12V Lateral to 800V Vertical Power Delivery
Traditional servers mostly adopt 12V power supply, but under the pressure of high current in AI computing, line losses (I²R) are increasing geometrically.
To reduce wiring current and improve conversion efficiency, AI data centers are undergoing a stepped evolution in supply voltage: leaping from the traditional 12V to 48V, and further advancing towards direct power supply of ±400V DC or 800V DC.
In addition to the continuously climbing voltage, the physical structure of the power layout is also undergoing fundamental changes:
Source: Murata
- Lateral Power Delivery (Current): Power conversion modules are placed around the chip, with a switching frequency of about 2 MHz, resulting in long wiring paths and high losses.
- Vertical Power Delivery (Near Future): Power modules are moved directly under the chip, with the switching frequency increased to 8 MHz. The current path is shortened, significantly reducing wiring losses.
- In-Package Integrated Voltage Regulator IVR (Future): The switching frequency surges to 110 MHz. The PDN is extremely compressed in the last mile to maximize the chip's ultimate performance.
Xie Zhewei, Manager of the Technical Section, Strategic Marketing Sales Department 1, Murata China, pointed out that this high-frequency, high-density architectural reconstruction poses extremely stringent challenges to passive components. For instance, the heat resistance limit of components must be increased from the original 85°C to 105°C or even 120°C, and they must feature ultra-low equivalent series inductance (ESL) to suppress voltage fluctuations. This is because, under the current transients of hundreds or even thousands of watts in AI chips, even a minor voltage ripple in the PDN could lead to chip calculation errors or even system crashes.
To address this challenge, Murata has launched multi-dimensional capacitor and inductor solutions spanning from PCBs and substrates to in-chip embedding, building upon its original layout:
- PAC Polymer Aluminum Electrolytic Capacitors: Placed at the board-level low-frequency decoupling (100 kHz stage), featuring ultra-low ESR (4.5 mΩ). The unique aluminum foil structure is safer and less prone to combustion than traditional tantalum capacitors, providing robust backup power and ripple smoothing capabilities.
- Low ESL Three-Terminal and LL Series MLCCs: Targeted at high-density mounting (1 MHz stage), the current path is shortened by altering the electrode structure, significantly reducing the equivalent series inductance (OESL). This achieves lower impedance with fewer components.
- Integrated Package Solutions: With a thickness of only about 300-350 µm and a capacitance density between 2.3 and 3.0 µF/mm², these are specifically designed for vertical power delivery (VPD). They are directly embedded within the package substrate, featuring internal vertical vias that allow the current path to penetrate "top-to-bottom" over the shortest distance, demonstrating extremely wide impedance suppression capabilities across a bandwidth from several MHz to several hundred MHz.
- High-Density 3D Silicon Capacitors (SC Series): Utilizing semiconductor MOS processes to build a 3D architecture in ultra-thin chips under 100 µm, doubling the volumetric density. These are specifically designed for in-package decoupling at high bandwidths (1 GHz stage) for single channels above 200G.
- Ultra-Thin Embedded Inductors (300 µm): In conjunction with future in-package integrated voltage regulator (IVR/IDR) technology, Murata has successfully developed power inductors into ultra-thin types of about 300 µm or direct embedded types. Placed closely against the chip die, they completely eliminate surrounding stray inductance, perfectly locking down voltage fluctuations.
Passive components are a rigid demand in the AI era. According to data shared by Wu Yueheng, General Manager of the Computing Market Sales Department, Murata China, in a current mainstream AI server (including the motherboard and accelerator cards), the capacitor usage alone reaches up to 20,000 units. Some customers with higher redundancy designs even use 30,000 to 50,000 units.
How to Break Through the Electrical and Optical Bottlenecks of High-Speed Optical Modules?
Within data centers, the surge in computing power also imposes "oppressive" upgrade requirements on data transmission speeds. AI clusters are driving optical module rates to climb continuously, undergoing rapid technological iterations from 400G and 800G to 1.6T and even 3.2T.
Yole Group estimates that the global data communication optical module market will surge from 18 billion USD in 2025 to break through the 110 billion USD mark by 2031, at a high compound annual growth rate (CAGR) of 33%. Meanwhile, the update cycle for traditional pluggable optical modules will be significantly shortened from the previous 3-4 years to 1-2 years.
Source: Murata
However, when optical modules attempt to achieve maximum rate transmission within the limited OSFP standard package size, they are facing four major physical limit challenges:
- High Bandwidth Limitations: The single-channel rate is evolving from 50G/100G to 200G/400G, which is approaching the physical limits of existing modulation technologies and optoelectronic materials.
- Signal Integrity Collapse: At ultra-high rates, minor impedance discontinuities cause a dramatic increase in losses in PCBs and connectors, leading to a surge in bit error rates.
- Extreme Space Constraints: With the number of channels doubling, high-speed signal lines are extremely dense, leaving almost no room for routing.
- Thermal Management Failure: When the power consumption of a single optical module breaks through the limit point, traditional air cooling completely fails. Complex liquid cooling (such as the XPO architecture, where a single module's bandwidth can reach 12.8 Tbps) must be introduced, or it must evolve towards Near-Packaged Optics (NPO) and Co-Packaged Optics (CPO).
Addressing the electrical and optical bottlenecks inside optical modules, Wu Yueheng revealed that Murata has started from underlying materials and cutting-edge optics to propose a series of innovative solutions:
- X2SC: In the AC coupling of signal lines (on PCB), traditional MLCCs generate high insertion loss (IL). Murata's new broadband silicon capacitor supports ultra-high bandwidth up to 220 GHz and differential transmission modes. Its bottom electrode design eliminates the need for side solder wicking, saving up to 70% of board space for optical modules, perfectly solving the dual problems of space and signal loss.
- Wire-Bond Capacitors and Custom Silicon Substrates: Inside TOSA/ROSA, Murata provides ultra-thin (100 µm) silicon wire-bond capacitors and small-size, high-capacity ceramic wire-bond capacitors. Furthermore, Murata utilizes Silicon Integrated Passive Device (IPD) technology to integrate originally separate capacitors and resistors into a single "R, C integrated silicon interposer (silicon substrate)," supporting single-lane 200G and above solutions, significantly reducing assembly time and achieving ultimate miniaturization.
In addition, Murata is also developing innovative material products suitable for optical modules, including Thin Film Lithium Niobate (TFLN) electro-optic modulators, Ceramic Fiber Couplers (CFC), LTCC substrates, and organic electrical and optical substrates such as LCP.
Thermal Management and Micro-Clock Innovations Build a Safety Line for Computing Cores
After solving the challenges of power transmission and data channels, real-time monitoring and heat dissipation inside the server become the last line of defense. As cooling methods transition from air cooling to liquid cooling, cooling passive components in deteriorating airflow environments becomes more difficult.
In this field, Murata has also launched competitive products and solutions:
- Precision Thermistors (NCU/PRF/PRG Series): As the chip TDP surges, Murata recommends placing high-reliability NTC thermistors in 1005/0201 sizes directly next to or under the chip die for real-time, accurate, and rapid hotspot monitoring, working with control circuits to execute fan startup or frequency reduction protection. Meanwhile, their PTC thermistors can serve as high-reliability resettable fuses, providing consistent overcurrent protection for IC packages.
- Fine-Shaped Processed Foil Wick: The wicks in traditional vapor chambers mostly use metal mesh or metal powder sintering, which limits further thickness compression. Murata innovatively uses fine-shaped processed foil as the wick, which has several times the capillary force of traditional metal mesh. They have successfully developed ultra-thin vapor chambers with a thickness of less than 200 µm. These achieve excellent thermal uniformity even under extremely high heat input, making them highly suitable for high-power-density scenarios such as smartphones, tablets, laptops, and optical modules.
- Micro Passive Crystals: Around high-speed optical modules and DSP chips, traditional designs mostly use high-cost active oscillators (Osc). Murata, in joint recommendation with well-known foreign DSP chip manufacturers, advocates for passive crystal solutions, which not only effectively reduce clock jitter but also significantly lower clock costs. Most importantly, Murata's passive crystal series adopts an exclusive patented single-layer ceramic resin sealing ring structure (Single layer ceramic "plate"), eliminating inorganic particle failures and keeping the field failure rate below 1 ppb. With a factory lead time of only 8 weeks (compared to 18-20 weeks for traditional manufacturers), it provides the strongest delivery guarantee for the compact AI supply chain.
Conclusion
Looking at Murata's comprehensive passive hardware layout in the AI era, it is not difficult to see that this traditional Japanese giant is undergoing a profound organizational and strategic transformation.
In the past, electronic component manufacturers mostly adopted a passive model of "serving wherever market orders come from." However, in the era of drastic AI transformation where technology update cycles are shortened to 1-2 years, this lagging R&D model will be eliminated by the market.
Wu Yueheng revealed in the interview that Murata's biggest change in the past two years is establishing dedicated organizations to directly interface with advanced IC and IT chip suppliers and system integrators globally and in China, 2-3 years before mass production (i.e., during the early reference design and concept stages of chip design).
Xie Zhewei further pointed out that Murata is leveraging its leading analysis and analytical capabilities to pre-program and package the S-parameters and SPICE models of components such as capacitors and inductors, embedding them into the customers' EDA system tool libraries. Through full-chain PDN simulation and IC matching evaluation (covering localized laboratories in Beijing, Shanghai, Shenzhen, Taipei, etc.), Murata assists chip giants in jointly defining power supply and signal integrity standards in the AI era at the initial stage of design.
This not only helps server and chip manufacturers shorten their R&D cycles by over 30% and optimize transient load responses, but also enables Murata to successfully transform its cutting-edge technologies into underlying industry standards and patent barriers.