Recently, the 16th International Nanotechnology Industry Expo was held at the Suzhou International Expo Center. During this expo, XinShiYe launched the "Q&A · NanoExpo" series of interview reports. This article features an exclusive interview with Pan Yao, General Manager of Suzhou MemsTech Semiconductor Technology Co., Ltd.
A layer of silicon, a layer of silicon dioxide, and another layer of silicon—this "three-layer sandwich" structure is essential for silicon photonics chips. According to Pan Yao, very few manufacturers globally have mass production capabilities. Amid the boom in silicon photonics, MemsTech's products are reportedly in short supply: they have achieved a certain scale of mass production and are currently planning and advancing a 12-inch SOI production line.
More notably, their silicon photonics SOI does not use ion implantation, bypassing the patent licensing route dominated by overseas manufacturers. What makes this domestic manufacturer, whose team has over 30 years of deep accumulation in the field, one of the few global players "not relying on licenses"? XinShiYe interviewed Pan Yao to reveal MemsTech's development path to industry readers.
The following interview content is organized based on on-site interviews, edited without changing the original meaning.
Q1: Please introduce your company's products?
Pan Yao: We produce silicon photonics interconnect SOI wafers and heterogeneous material bonding products. We are not a new company; our team has over 30 years of deep accumulation in this field. As far as I know, very few manufacturers globally have mass production capabilities because the technical barriers are high and replication is difficult.
Although called "wafers," our products undergo 10 process steps and are standard products with a "three-layer sandwich" structure—two layers of silicon with a silicon dioxide insulating layer in between, with bonding being the core. We only produce engineering substrates and do not manufacture devices; downstream customers buy the substrates to tape out and make devices.
Q2: What are the main application directions for SOI wafers? Why is it "indispensable" for the silicon photonics industry?
Pan Yao: In the past, our products were mainly used in RF filtering and MEMS fields, such as gyroscopes, inertial devices, accelerometers, micro-mirrors, and the now popular OCS optical switches—their core micro-mirror arrays are derivatives of micro-mirrors.
Now that silicon photonics is booming, we are shifting more towards silicon photonics. The silicon photonics industry must use SOI: light propagation requires the middle silicon dioxide insulating layer, so SOI is a necessity and irreplaceable in silicon photonics interconnects. Other industries can flourish using ordinary silicon wafers; however, using SOI reduces parasitic capacitance and improves yield, a point already recognized by the market.
Q3: What is the difference between silicon photonics SOI and traditional SOI? Why can your company "avoid ion implantation"?
Pan Yao: For us, making products for silicon photonics is almost the same as our original products, except for the thickness of the top silicon—also known as the device layer: silicon photonics requires thinner layers, which is precisely our unique strength.
From a process perspective, we do not need ion implantation for silicon photonics; we have formed a differentiated process path: Traditional routes mostly adopt ion implantation, with related patent layouts concentrated among overseas manufacturers. Domestic or other countries often need to obtain authorization to use them.
We can achieve this because our process has made breakthroughs: The device layer can be made thinner using Chemical Mechanical Polishing (CMP), achieving top silicon uniformity within ±0.1 microns; device layer thicknesses between 100 nanometers and 2 microns can avoid ion implantation, whereas other routes in the industry mostly adopt ion implantation for thicknesses below 2 microns.
Q4: Are SOI wafers a "high-end business"? How do you balance costs?
Pan Yao: Our products are used to make high-end devices, with selling prices 20 to 30 times that of ordinary silicon wafers. However, material cost is negligible for the final device, and the yield improvement brought by SOI is often more worthwhile than the increased material cost.
We also have a natural advantage in yield control: An ion implantation equipment alone costs CNY 50 million, while we use polishing methods, significantly reducing costs and improving efficiency. We have competitive space on the cost side.
Q5: What are the current capacity and expansion plans?
Pan Yao: Currently, we have formed a certain scale of mass production, with the production line located in Suzhou Nano City. At this stage, silicon photonics is hot, and the entire industry is a seller's market with supply falling short of demand. We are currently planning and advancing a 12-inch SOI wafer production line. The difficulties in expansion are mainly funding and talent—large-scale manufacturing requires significant capital investment, and the equipment itself is expensive; but we are not starting from scratch, having polished the technology for30 years.
Q6: What is the technical judgment behind cooperation with domestic material enterprises? What challenges does heterogeneous bonding face?
Pan Yao: SOI is just a single product; heterogeneous material bonding is the direction where we see greater potential: New materials will continue to emerge, such as Gallium Oxide (Ga2O3) in fourth-generation semiconductors, which was very expensive when it first appeared. By bonding the characteristics of new materials with ordinary silicon, we can reduce costs and "complement strengths," integrating the characteristics of new materials into other products.
We have reached strategic cooperation with domestic Ga2O3 material enterprises. Heterogeneous bonding faces great challenges: SOI uses high-temperature bonding at 1200°C, while heterogeneous material bonding must be controlled within low-temperature bonding under 200°C. Ensuring bonding strength at low temperatures is the core difficulty. Currently, we can bond more than ten types of heterogeneous materials, such as Silicon Nitride with Lithium Niobate, and Ga2O3 with Silicon. Some solutions have been delivered to customers, the technology is mature, saving R&D time and greatly shortening delivery cycles, with deliveries completed in 1-2 weeks.
Q7: How do your products gain recognition from international top-tier customers? How do overseas clients land?
Pan Yao: Our team has over 30 years of deep accumulation in this field and a strong R&D foundation. We cooperate with multiple well-known overseas chip and system vendors. Overseas clients are relatively standard and direct in matching specifications. This industry is a seller's market; as long as the produced products meet customer specifications, customers will adopt them without lengthy certification processes. In the future, we hope to combine our overseas R&D accumulation with domestic capacity to serve more enterprise clients both domestically and internationally.
Q8: What is the current status of the domestic SOI industrial chain? What shortcomings remain upstream and downstream?
Pan Yao: Globally, very few SOI manufacturers have mass production capabilities. Previously, some domestic manufacturers adopted the overseas licensing route, while our team relies on over 30 years of deep cultivation to follow an independent, self-developed differentiated path.
The good news is that equipment and raw materials are not restricted. We currently use a combination of imported and domestic equipment; core processes like grinding, polishing, and bonding use imported equipment, while cleaning, metrology, and oxidation processes have been localized. Raw materials are ordinary silicon wafers, widely supplied domestically and directly procurable.
What is truly scarce is the deep processing capability for new materials. Currently, domestic investment is heavy in areas like equipment and foundries, but layout for deep processing of new materials like SOI and heterogeneous bonding is relatively blank. High-value-added processing links mostly remain overseas, which is the situation we aim to change upon returning to China.
Q9: Why did you choose to return to China? What are your upcoming plans for financing and exhibitions?
Pan Yao: China is a huge market, and clients have demands. In 2012, due to the lack of application scenarios at the time, our partners temporarily abandoned this project and chose to start businesses in the US; in 2021, we returned with the same project and landed in China this time—because domestic chip manufacturing capabilities have improved significantly, and the market has driven up the demand for SOI. At this stage, it can be described as a boom where "capacity equals sales."
This is already our third participation in the NanoExpo, and we have won awards from the exhibition organizers' competitions. This time, we hope to let more people know: Our SOI technology is different from peers, and we have a strong first-mover advantage in the field of heterogeneous material bonding. Because of our technological leadership, we can help customers achieve more new chip capabilities. Regarding financing, we have obtained early-stage funding support and are currently continuously engaging with the capital market.