Semiconductor Storage Layer counts are still increasing, but major players have already opened up new battlegrounds. From August 4 to 6 local time, FMS 2026 was held at the Santa Clara Convention Center in California, USA. This annual storage technology-focused industry conference released signals this year somewhat different from those of previous years.
Layer stacking in the storage field continues to advance: Samsung released the industry's first V10 BV-NAND exceeding 400 layers, SK hynix unveiled its 10th-generation 375-layer 4D NAND for the first time, and Kioxia and SanDisk jointly launched the 332-layer BiCS10 QLC NAND. However, if you only focus on layer counts, you might miss the truly important signals at this FMS. Storage giants are answering the same question with completely different technological routes: how to get data to computing power faster.
Samsung is betting on wafer bonding and vertical stacking. SK hynix has joined forces with SanDisk to open up a new tier named HBF between HBM (High Bandwidth Memory) and SSDs (Solid State Drives). Kioxia and Micron have chosen to use the CXL (Compute Express Link) protocol to break the boundaries between memory and storage. Beyond the divergence in routes, controller chip manufacturers are fully ready for PCIe (Peripheral Component Interconnect Express) 6.0, paving the way for the scaled production of SSDs. Meanwhile, domestic manufacturers are actively making efforts in areas such as edge AI deployment, storage computing chips, and CXL.
I. Layer Counts Continue to Advance, but Are No Longer the Protagonist Samsung, SK hynix, Kioxia, and SanDisk all showcased next-generation NAND flash products at FMS 2026, with breakthroughs in layer counts. However, the true focus at each booth is no longer on 'who has a higher layer count.'
FMS 2026: An Overview of Partial Technological Routes of Storage Manufacturers Samsung officially unveiled its 10th-generation V-NAND, the V10 BV-NAND, marking another milestone since the pioneering of V-NAND in 2013. This product adopts a brand-new wafer bonding architecture, with stacking layers breaking through 400. The storage density is improved by approximately 58% compared to the previous generation V9, with significant enhancements in read, write, and I/O performance. However, Samsung's core narrative at the exhibition is not '400 layers,' but 'wafer bonding.' This breakthrough at the manufacturing process level is the true technical core of the V10 BV-NAND.
SK hynix publicly displayed its 10th-generation 375-layer 4D NAND flash wafers and products at its booth for the first time. Its performance-per-watt is improved by 2.5 times compared to the previous generation. The company plans to start mass production of high-performance, large-capacity enterprise SSDs based on this flash memory in early 2027. However, what attracted the most attention for SK hynix at FMS was not just this 375-layer NAND, but another independently released technology—the HBF standard specification.
Kioxia and SanDisk jointly launched the 10th-generation BiCS FLASH 3D QLC NAND, adopting a CBA (CMOS Bonding Array) architecture, achieving 332-layer stacking, an areal density of 37GB/mm2, and an interface speed of 4800MT/s. This product is positioned for data center AI SSDs, focusing on optimizing the large-capacity cache requirements of KV-Cache. Meanwhile, Kioxia introduced its first enterprise SSD using 10th-generation BiCS flash memory—the CM10 series, which supports direct liquid cooling and is specifically designed for AI and modern data center environments.
The layer-count race has not stopped, but it is no longer the core dimension defining industry leadership. After stacking layers break through 400, manufacturers' focus is shifting from 'how many layers can be stacked' to 'how to make flash memory serve AI computing faster and more efficiently.' Wafer bonding, architectural innovation, and energy efficiency optimization have become the true keywords for NAND technology at FMS 2026.
II. Three Routes Pointing to Similar Goals If the layer-count race served as the main thread for the storage industry over the past decade, FMS 2026 showcases the new landscape for the decade ahead. Storage giants have chosen three different technological paths to solve the same problem: the memory and storage bottleneck in the AI era.
The First Route: Continuing to Climb in Vertical Stacking. Samsung unveiled two conceptual models, zHBM and zNAND-O, for the first time at FMS 2026. zHBM vertically stacks HBM on top of AI accelerators, rather than placing them side by side as in traditional setups. Compared to traditional HBM architectures, the data transmission distance is significantly shortened. Its performance can reach about 8 times that of the next-generation HBM5, energy efficiency is improved by 3 times, thermal resistance is reduced by more than half, and it supports customer-customized IP integration. zNAND-O, on the other hand, targets edge AI environments, developing 4-layer and 8-layer versions, focusing on low latency and high I/O (Input/Output) performance to fill the gap in the demand for high-performance storage media in edge-side inference. [Related Reading]
The Second Route: Opening Up a New Tier Between HBM and SSDs. On the first day of FMS 2026, SK hynix announced a joint venture with SanDisk to officially release the first standard specification for High Bandwidth Flash (HBF). HBF is a new storage tier between HBM and SSDs, combining the high-speed data transmission capability of HBM with the large-capacity scalability of NAND. [Related Reading]
The specification defines two capacity configurations—8-layer and 16-layer NAND chip stacking, supporting up to 512GB capacity. It also sets bandwidth standards across three tiers, with data transmission capabilities covering approximately 0.4TB/s to 3.0TB/s. HBF uses the industry-standard UCIe interconnect with processors, laying the foundation for flexible connections with different types of processors such as GPUs and CPUs. This specification was officially released by the OCP, the world's largest open data center technology organization, becoming an industry-wide open standard rather than a proprietary enterprise standard. Currently, the HBF alliance has gathered Google and Tenstorrent.
The Third Route: Using CXL to Break the Boundaries Between Memory and Storage. Kioxia focused on showcasing the GP series high-IOPS (Input/Output Operations Per Second) SSDs optimized for direct GPU access, as well as the CM10 series enterprise SSDs, the first to use 10th-generation BiCS flash memory and support direct liquid cooling at FMS 2026. Meanwhile, Micron showcased a CXL-based memory pooling solution, deploying near-data processing capabilities on the memory side to reduce data movement overhead, and jointly explored the application of PCIe Gen 6 in AI data center storage architectures with industry partners.
Beyond the three routes, there is also a 'game-changer' path. 3D storage semiconductor IP company NEO Semiconductor released X-SRAM (Static Random Access Memory) technology at FMS 2026—a dual-transistor SRAM design that can provide up to 5 times the on-chip cache density of traditional SRAM, increasing the built-in memory capacity of AI chips from the current approximately 200-400MB to 1-2GB, while reducing HBM access power consumption by about 50% to 80%. Its other technology, 3D X-DRAM (Dynamic Random Access Memory), can increase HBM capacity to 10 times that of traditional DRAM.
NEO represents a path different from the big three, not relying on manufacturing capacity, but driving storage architecture innovation through a technology licensing model.
The big three each take their own path, while NEO strikes from the side. The signal conveyed by FMS 2026 is that the storage industry is moving from a 'single track' to 'multiple parallel routes.' Which route ultimately wins will be determined by the choices made in the actual deployment of AI data centers.
III. Controller Chips and Other Products Are Ready; Domestic Manufacturers Are Also Actively Making Efforts Behind the technological routes, controller chips are needed for support. At FMS 2026, the intensive releases from controller manufacturers indicate that the scaled deployment of PCIe 6.0 SSDs has entered the countdown.
Silicon Motion showcased the enterprise PCIe 6.0 controller SM8466, supporting 28GB/s sequential read and 7 million IOPS random performance, with a single drive capacity of up to 512TB, planned for mass production within 2026.
Innogrit demonstrated for the first time two controller chips for next-generation AI infrastructure: an enterprise PCIe 6.0 SSD controller and a CXL Type 3 controller. Its PCIe 6.0 solution can achieve 10M IOPS for 512-byte random read performance. The CXL controller supports CXL 3.1, and the CXL module capacity based on NAND particles can reach 512GB.
ScaleFlux released the PCIe Gen6 controller FC6116 and the CXL 3.2 memory controller MC600, both planned for sampling in Q4 2026. Marvell announced the PCIe Gen6 controller Bravera SC6, planned for sampling in Q4. FADU launched the PCIe 6.0 enterprise controller FC6161, also planned for sampling in Q4.
The collective readiness of controller chips means that the conditions for mass production of PCIe 6.0 enterprise SSDs are rapidly maturing. Judging from the timetables of various companies, the end of 2026 to the first half of 2027 will usher in a concentrated shipment period for PCIe 6.0 SSDs.
The exhibition lineup of other storage manufacturers is equally noteworthy. Longsys showcased its edge AI solution jointly developed with AMD and its self-developed controller PCIe 5.0 SSD. Biwin exhibited enterprise PCIe Gen5 SSDs and automotive-grade storage products.
DapuStor and UBIX jointly submitted the UbiPower 18000 solution, which was shortlisted for the final round of the FMS 2026 Device Engineering Award. This solution is based on DapuStor's full-stack self-developed Rongshen R6 series enterprise NVMe (Non-Volatile Memory Express) SSDs, completing full-link collaborative optimization for AI large model training and ultra-long context inference scenarios.
KOWIN Semiconductor exhibited embedded storage, SSDs, DRAM, and mobile storage products: the Small PKG. eMMC/ePOP solution is adapted for lightweight terminals such as AI glasses and smartwatches; industrial-grade wide-temperature eMMC is targeted at industrial PCs and edge industrial control; SSD products are aimed at Mini PCs and edge computing hosts; DRAM modules are adapted for AI laptops and desktop computers; and mobile storage meets the needs of offline storage and cross-device data flow for AI terminals.
YEESTOR Microelectronics presented a full-scenario AI storage computing product matrix based on three major technical pillars: 'storage control, storage-computing interconnection, and storage-computing integration.' Among them, the PCIe Gen5 SSD storage computing controller YS9503 achieves a sequential read performance of 14.8GB/s. The product solutions cover five major fields: AI PC, AI smartphone, smart vehicles, smart industry, and AI Infra, comprehensively demonstrating the storage computing innovation strength from chips to systems.
Montage Technology announced on the eve of FMS that it has taken the lead in trial production of the CXL 3.2 Memory Expander Controller (MXC), supporting PCIe 6.x and CXL 3.2 protocols, with a maximum speed of 64 GT/s, and integrating dual DDR5 memory controllers. This product has been introduced into the next-generation CXL products of leading memory module manufacturers such as Samsung, and has completed preliminary verification.
The signal conveyed by FMS 2026 is clear and strong: the storage industry is bidding farewell to the single narrative of the 'layer-count race.' Of course, layer count remains one of the important indicators for measuring NAND technology iteration. However, after stacking layers break through 400, the industry's focus is expanding from 'how many layers can be stacked' to more dimensions. How to make flash memory serve AI computing faster and more efficiently is becoming a proposition as important as layer count.
The next decade of the storage industry may belong not only to 'who can stack more layers,' but more importantly to 'how to make data flow faster, closer, and smarter.'
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