I. First-Day Surge of 28.38% Pushes Market Cap Past HKD 12.1 Billion
On November 10, 2026, the Hong Kong stock market's semiconductor and AI computing hardware sectors welcomed a heavyweight new entrant. Jiangsu Xinde Semiconductor Technology Co., Ltd. (abbreviated as "JSSI," Stock Code: 07672.HK), a leading advanced packaging and testing enterprise headquartered in the Pukou Economic Development Zone of Nanjing, Jiangsu Province, officially listed on the Main Board of the Hong Kong Stock Exchange (with Huatai International serving as the sole sponsor). In this global offering, JSSI issued 106.56 million H-shares (90% international placement, 10% public offer in Hong Kong), with a final offer price set at HKD 8.88 per share. The total gross proceeds from the global offering amounted to approximately HKD 946 million, with net proceeds after deducting issuance expenses ranging from HKD 882 million to HKD 904 million. On its first trading day, JSSI opened 20.50% higher at HKD 10.70 per share. Riding the bullish sentiment in the Hong Kong semiconductor sector, the stock briefly surged over 30% during intraday trading before closing at HKD 11.40 per share. This resulted in a first-day gain of 28.38%, pushing its total market capitalization past the HKD 10 billion mark to settle at HKD 12.148 billion, making it the "First Hard-Tech IPO from Nanjing Pukou".
Founded in September 2020, how did JSSI manage to become a Forbes China Unicorn within just six years and secure a high valuation exceeding HKD 12.1 billion on its IPO debut? A review of JSSI's prospectus reveals a luxurious three-dimensional ecosystem composed of a "top-tier OSAT veteran team + chip/terminal giant shareholders + semiconductor equipment leader cornerstone investors":
● Led by core teams from JCET Advanced and Amkor, with over 30 years of experience in advanced packaging and testing: Zhang Guodong, Chairman and Executive Director of JSSI, previously served as a director at JCET Advanced. Co-founder and General Manager Pan Mingdong, along with the core executive team, hails from global top-tier OSATs such as JCET and Amkor. They possess over 30 years of engineering mass production and yield ramp-up experience in Wafer Bumping, Flip-Chip, and Wafer-Level Packaging (WLP). Post-listing, Zhang Guodong, Pan Mingdong, Liu Yi, and the employee stock ownership platform act as concerted parties, collectively controlling approximately 22.45% of the company's shares, forming the single largest shareholder group.
● Strategic investment by terminal and chip giants like Xiaomi, OPPO, and MediaTek deeply locks in downstream demand: Over six years, JSSI completed seven rounds of financing, attracting not only renowned institutions such as Chenyi Fund (holding 6.76%, largest institutional shareholder), Nanjing Innovation Investment Group (holding 6.10%), Yuanhe Puhua, and Kunqiao Capital, but also directly introducing three major smartphone and SoC chip giants—Xiaomi Changjiang Industrial Fund (holding 2.61%), OPPO (holding 1.14%), and MediaTek (holding 0.31%)—as strategic shareholders. On the business side, it deeply serves core clients such as display driver chip leader Chipone and RF front-end small giant Raystone Micro (in the first four months of 2026, the top five customers contributed 55.0% of revenue).
● Three cornerstone investors locked in over 32% of offered shares; equipment leader MaxWell invested CNY 100 million to build an equipment-packaging synergy loop: In this IPO, GF Fund (subscribing USD 15 million/approx. HKD 117.7 million), Guohui Hong Kong (subscribing USD 10 million/approx. HKD 78.478 million), and Maxwell Technology, the wholly-owned Singapore subsidiary of domestic pan-semiconductor laser and bonding equipment leader MaxWell (300751.SZ) (subscribing equivalent to CNY 100 million/approx. HKD 116.8 million), collectively subscribed for HKD 313 million, accounting for over 32% of the global offering. As pointed out in our previous reports on glass substrates and temporary bonding/debonding (TBDB), MaxWell is aggressively entering the fields of semiconductor wafer thinning, laser modification/delamination, and hybrid bonding equipment. Its heavy investment as a cornerstone investor strategically binds JSSI, creating an imaginative closed loop of "R&D of domestic high-end packaging equipment + verification and volume production on local advanced packaging lines."
II. One of the Few Domestic OSATs Capable of Integrating QFN/BGA/WLP/2.5D/3D
In the independent Outsourced Semiconductor Assembly and Test (OSAT) sector, most startups face a cruel "binary choice" dilemma: either stick to low-barrier traditional wire-bonding (Wire-Bond QFN/SOP), falling into fierce price wars and unable to penetrate high-computing chips; or focus solely on single wafer bumping or 2.5D mid-end manufacturing, lacking back-end substrate packaging (BGA/LGA) and final test capabilities, thus failing to provide one-stop Turnkey delivery to IC design customers. JSSI has become one of the very few manufacturers in mainland China possessing simultaneous mass production capabilities across QFN, BGA, LGA, WLP (Wafer-Level Packaging), and 2.5D/3D full-category advanced packaging. The core reason lies in its foundational technical anchor of "Bumping + Flip-Chip" established since inception, building upwards to connect five major product matrices:
1. High-Order Flip-Chip QFN (FC-QFN, 2025 Revenue CNY 313 million, Share 30.9%): Unlike traditional gold-wire bonded low-end QFN, JSSI focuses on FC-QFN and FC-SOT based on Copper Pillar Bumps. By electroplating high-density copper pillars on the wafer surface and directly flip-chip reflow soldering them onto lead frames, parasitic inductance caused by high-arc gold wires is eliminated (inductance reduced by over 50%), while heat can be efficiently dissipated through exposed pads on the chip backside. With the scaled-up volume production at the Nanjing base, the gross margin of the company's QFN product line significantly improved in 2025~2026, becoming the primary pillar supporting cash flow.
2. High-Density Flip-Chip BGA (FC-BGA / FCCSP, 2025 Revenue CNY 306 million, Share 30.3%): Targeting general-purpose processors, edge-side AI SoCs, and high-speed network switch chips, JSSI has built mature mass production lines for multi-layer BT/ABF substrate flip-chip BGAs. These support fine-pitch bumps, mounting of high-density passive R/C components (01005/008004 SMD) on chip surfaces, and packaging with high-thermal-conductivity Heat Spreader Lids. In 2025, its BGA business revenue reached CNY 306 million, keeping pace with QFN.
3. 5G RF High-Density SiP-LGA Modules (2025 Revenue CNY 213 million, Share 21.0%): Addressing smartphone 5G/5G-A RF front-end Power Amplifiers (PA), filters, and Front-End Modules (FEM), JSSI established dedicated high-density System-in-Package (SiP-LGA) lines at its Nanjing and newly built Yangzhou bases. These support multi-chip heterogeneous mixing, double-sided molding, laser grooving, and sputtered EMI Shielding, deeply binding with domestic RF leaders like Raystone Micro.
4. 12-Inch Wafer-Level Packaging WLP (Bumping / WLCSP / Fan-Out, 2025 Revenue CNY 177 million, Share 17.5%): WLP is the critical Mid-End-of-Line (MEOL) connecting front-end wafer manufacturing and back-end 2.5D/3D packaging. JSSI fully masters 12-inch wafer Au Bumps, CuNiAu bumps, micro-solder ball placement, multi-layer polymer/copper Redistribution Layers (RDL), Wafer-Level Chip Scale Packages (WLCSP), and Fan-Out WLP (FOWLP), providing a fully autonomous MEOL process foundation for transitioning to higher-order 2.5D/3D heterogeneous integration.
5. 2.5D/3D Chiplet Heterogeneous Integration and Full-Process Testing Services: Leveraging the accumulated mid-back-end processes of the previous four categories, JSSI naturally extended upstream to enable 2.5D/3D packaging based on RDL interposers, TSV silicon interposers, and TGV glass substrates. According to the prospectus, JSSI's total advanced packaging revenue reached CNY 737 million in 2025, accounting for 72.8% of total revenue (CNY 1.012 billion). Its purity in advanced packaging ranks among the top comparable OSAT peers in both A-share and HK markets.
III. How the Self-Developed CAPiC Platform Connects TGV Glass Substrates, LPDDR, and CPO Co-Packaged Optics
If QFN, BGA, LGA, and WLP constitute the billion-revenue baseline for JSSI, then the self-developed CAPiC (Chiplet Advanced Packaging in Chip) platform, launched in March 2023 and continuously iterated, is the core technological trump card that enabled the capital market to assign it a market cap of HKD 12.148 billion (approximately 17.6% of the net IPO proceeds, or HKD 159 million, was explicitly allocated to advancing CAPiC platform R&D). Addressing the pain points of post-Moore era AI computing power, high-bandwidth memory, and ultra-high-speed optical interconnects, the CAPiC platform constructs four cutting-edge technical sub-architectures:
1. CAPiC-LDFO and 2.5D/3D Heterogeneous Integration Architecture (Awarded BroadPak Excellence Award in the US): In traditional CoWoS-S packaging, the entire TSV silicon interposer is extremely costly and constrained by foundry capacity scheduling. JSSI's CAPiC platform innovatively introduces Large-Dimension Fan-Out (LDFO) and Multi-Layer RDL Interposer technologies. By first fabricating multi-layer high-density copper RDL interposers with sub-micron to 2μm line width/space on temporary glass carriers (RDL-first), replacing expensive silicon interposers or traditional substrates, multiple logic chiplets (SoCs) and companion chiplets are then flip-chip bonded onto them. In the benchmark project that won the US BroadPak Excellence Award, the JSSI team successfully reduced contact resistance at connection interfaces to milliohm levels using RDL Interposers and achieved optimal performance-cost balance by densely mounting miniaturized decoupling capacitors on the wafer surface to overcome high-speed DC blocking challenges.
2. CAPiC-TGV Glass Substrate and Glass Embedded Packaging Architecture: As argued in our previous article "In-Depth Analysis of Glass Core Substrates," glass-based packaging is the ultimate solution for solving warpage and high-frequency loss in large-computing chips. JSSI proactively positioned itself in "Glass Embedding" and "2.5D TGV Glass Interposers" between 2023 and 2025 (Nanjing Venture Capital Group confirmed the company has built multiple advanced packaging platforms including 2.5D/3D, TGV, TMV, and LPDDR). Under the CAPiC-TGV architecture, JSSI leverages the high-frequency low-loss characteristics (tanδ < 0.005) and high rigidity (Young's Modulus 70~80 GPa) of TGV glass vias to construct 2.5D glass interposers. Simultaneously, it developed a 3D integration process where passive filter devices or small chips are embedded directly into cavities within the glass substrate, followed by dual-side RDL layer buildup, demonstrating strong competitiveness in millimeter-wave RF front-ends and large-size AI computing chips.
3. CAPiC-Memory High-End Storage Packaging (Covering LPDDR Ultra-Thin Stacked Die and TMV Vertical Interconnects): Facing vigorous demand for high-bandwidth low-power memory LPDDR5X/LPDDR6 in AI edge devices (AI phones, AI PCs) and cloud HBM co-packaging, JSSI's CAPiC platform constructed a comprehensive storage packaging and testing matrix. For LPDDR, the company integrates 12-inch ultra-thin wafer grinding, laser stealth dicing, multi-layer ultra-thin bare die step stacking, Flip-Chip, and Through-Mold Via (TMV) vertical interconnect processes, supporting ultra-thin stacked Package-on-Package (PoP) for mobile SoCs and LPDDR granules, as well as high-density WBGA/FCCSP discrete memory packaging. For cloud storage, the 2.5D silicon interposer and RDL interposer platforms under CAPiC directly support high-density co-packaging of HBM high-bandwidth memory and AI logic chips.
4. CAPiC-CPO Co-Packaged Optics and High-Speed Optical Module Heterogeneous Integration Platform: As AI computing cluster optical modules evolve from 800G to 1.6T/3.2T and Co-Packaged Optics (CPO), electrical interconnect loss and heat dissipation between high-speed DSP electrical chips and Silicon Photonics (SiPh PIC) modulators become the biggest bottlenecks. Leveraging the high-density RDL Interposer and micro-bump flip-chip processes awarded the BroadPak prize, JSSI's CAPiC-CPO platform co-packages high-power DSP chips, Transimpedance Amplifiers (TIA)/Drivers, high-density DC blocking capacitors, and silicon photonics engines on the same ultra-low-loss interposer base. Efficient heat extraction from localized high heat fluxes of DSP chips is achieved via customized high-thermal-conductivity Metallic Lids and Thermal Interface Materials (TIM). It has currently entered the supply chains of leading optical communication and high-performance computing customers.
IV. Revenue Doubling to CNY 1.012 Billion in Three Years: How Asset-Heavy Packaging Crosses Break-Even
Behind the cheers of JSSI's 28.38% first-day surge, the market closely watches a core financial contrast disclosed in its prospectus: rapid growth with revenue nearly doubling in two years versus cumulative losses of CNY 1.219 billion from 2023 to 2025 and negative gross margins indicating phase-specific book pressure. To understand JSSI's true investment value and industrial inflection point, one must look beyond the apparent income statement and calculate the underlying "Asset Depreciation and Utilization Rate Ramp-Up Formula" of the semiconductor advanced packaging industry (see Figure 4 below):
1. Revenue Side: CAGR of 41.0% over three years, with advanced packaging accounting for 72.8%, establishing a high-growth底色. Prospectus data shows that in 2023, 2024, and 2025, JSSI achieved operating revenues of CNY 509 million, CNY 827 million (+62.5% YoY), and CNY 1.012 billion (+22.4% YoY), respectively. The Compound Annual Growth Rate (CAGR) from 2023 to 2025 was 41.0%. Entering 2026, the company generated CNY 360 million in revenue in the first four months (Jan-Apr), continuing steady growth of 17.4% compared to CNY 306 million in the same period of 2025. According to Frost & Sullivan statistics, based on 2025 advanced packaging and testing revenue (CNY 737 million), JSSI, founded just over five years ago, has risen to become the seventh-largest general-purpose independent OSAT enterprise in China.
2. Profit and Gross Margin Side: Why still in gross loss despite breaking CNY 1 billion in revenue? Equipment depreciation and amortization at up to 33% is the sole primary cause. From 2023 to 2025, the company's annual losses were CNY -359 million, CNY -377 million, and CNY -483 million (loss of CNY -162 million in the first four months of 2026). However, a highly significant positive signal is that the overall gross loss rate narrowed sharply by 20.4 percentage points from -38.4% in 2023 to -18.0% in 2025! Why do asset-heavy packaging factories exhibit the phenomenon of "larger book depreciation losses with expansion, yet rapidly narrowing gross loss rates" during their growth phase?
As noted in our analysis of SJ Semiconductor, advanced packaging lines (especially12-inch Bumping lithography tools, plating lines, high-precision flip-chip bonders, and high-speed testers) require equipment investments often exceeding hundreds of millions of yuan per line. Accounting standards mandate rigid depreciation over 5~7 years once equipment is installed and transferred to fixed assets. In the first four months of 2026, depreciation and amortization alone accounted for 33.0% of JSSI's operating revenue! Currently, the company has two operational bases in Nanjing and Yangzhou. The Nanjing base (mainly producing QFN, BGA, LGA, WLP, 2.5D/3D) had a designed capacity of approx. 6.411 billion units in 2025, with actual output of 5.416 billion units, raising the capacity utilization rate to 84.5%. This drove the gross margin of mature advanced packaging like QFN to turn positive and improve first. The Yangzhou base (mainly producing high-density LGA modules, Phase I investment of CNY 1 billion, completed and operational in July 2025) had a capacity utilization rate of approx. 68.9% in the second half of 2025 and the first four months of 2026, still in the ramp-up phase crossing the 75%~80% break-even line.
3. Three Catalysts for Crossing the Break-Even Point (Positive Gross Margin in 2027, Clear Path to Operating Profitability in 2028): First, as the Yangzhou base's utilization rate ramps from 68.9% towards full load above 85%, the proportion of rigid depreciation relative to revenue will quickly dilute from 33% to below 20%. Second, upon receipt of the net HKD 882~904 million from the HK IPO, the company's balance sheet will be effectively optimized (replacing some interest-bearing bank loans, significantly reducing financial interest expenses). Third, high-unit-price, high-margin WLP wafer-level packaging and CAPiC 2.5D/3D, TGV, and CPO orders transitioning from sample verification to mass production will strongly boost the Average Selling Price (ASP) per packaged unit.
V. CNY 5.5 Billion Nanjing AI Packaging Base and the Rise of the Third Pole in Domestic Heterogeneous Integration
Standing at the new starting point of successfully listing on the HKEX in November 2026, JSSI's blueprint for capacity expansion and technical breakthroughs is fully laid out. According to the use of proceeds plan and major project progress disclosed in the company's prospectus:
1. 69.5% of Net Proceeds (approx. HKD 629 million) heavily invested in expanding advanced packaging lines; CNY 5.5 billion Nanjing AI Advanced Packaging Base accelerating implementation: The company directs nearly 70% of IPO proceeds directly to constructing production bases and purchasing high-end BGA, WLP, and 2.5D/3D production equipment. More critically, JSSI's "Artificial Intelligence Advanced Packaging and Testing Base Project," with a total investment of CNY 5.5 billion, has officially commenced construction in Pukou, Nanjing (Phase I investment of CNY 1 billion, planning 153,000 square meters of modern high-standard workshops). It comprehensively focuses on2.5D/3D Chiplet heterogeneous integration and high-density substrate packaging. Upon full capacity, it is expected to form massive production capabilities of 18,000 wafers of 2.5D heterogeneous integrated products and 300 million wafer-level high-density chips annually!
2. 17.6% of Net Proceeds (approx. HKD 159 million) specifically targeting CAPiC Platform, seizing next-generation standards for TGV and CPO: Approximately 8.8% is used to expand the top-tier packaging R&D team, while another 8.8% is specifically invested in process verification for Large-Dimension Fan-Out (LDFO), 2.5D/3D micro-bump/hybrid bonding, TGV glass substrates, and CPO co-packaged optics under the CAPiC platform (the remaining approx. 5.3% upgrades business and production digital management systems, and 7.6% supplements working capital).
3. Profound Implications for China's Advanced Packaging Industry: If JCET, TFME, and HT-Tech constitute the "First Pole (All-Round Aircraft Carriers)" of China's packaging industry, and SJ Semiconductor, Chengdu Yicheng, and Hubei Xingchen represent the "Second Pole (Special Heavy Weapons)" focusing on 2.5D silicon interposers or panel-level FO-MCM, then the "Third Pole (New Rising Full-Category Unicorns leveraging high-density FC-QFN/BGA/LGA cash flow as a shield and self-developed CAPiC 2.5D/TGV/CPO platforms as a spear)," represented by JSSI (07672.HK) and Forehope Electronic, is accelerating its rise through dual empowerment from HK and A-share capital markets. During the golden decade of AI computing chip localization and surging demand for HBM/LPDDR6/CPO packaging, this emerging force combining flexible customization mechanisms with full-stack advanced packaging capabilities will become an indispensable piece in China's semiconductor breakthrough against "post-Moore era" computing blockades.
[References and Authoritative Data Sources]
[1] Phoenix Finance: "Loss of CNY 1.2 Billion in Three Years; JSSI (07672.HK) Up 28% on First Day: Closing at HKD 11.40, Market Cap HKD 12.148 Billion, Deep Dive into Core Financials from Prospectus" (2026-11-10): https://finance.ifeng.com/c/8xx16q6o7Hd
[2] Phoenix Finance: "JSSI Lists on HKEX: Total Proceeds HKD 946 Million, Market Cap HKD 12.1 Billion, Revenue Nearly Doubled to CNY 1.012 Billion in Two Years" (2026-11-10): https://finance.ifeng.com/c/8xx0sIrFkz4
[3] Cailian Press: "Pessimistic Expectations for Computing Power Recover! HK Semiconductor Sector Strengthens, JSSI (07672.HK) Surges Over 30% Intraday on Listing Debut" (2026-11-10): https://www.cls.cn/detail/2530232