[Relevant Companies Involved in This Article] Intel, SK hynix, YMTC, Micron, Samsung, Kioxia, PSMC.
Intel Returns to Memory Manufacturing
This episode of TechSurge is packed with valuable insights. Facing the media, Lip-Bu Tan of Intel unveiled his new vision for Intel to regain its dominance in the CPU sector over the next decade. He emphasized that simply excelling in the core CPU business is no longer sufficient. In the future, Intel will undergo a comprehensive restructuring around computing, system architecture, high-bandwidth memory, and advanced system-level packaging, fostering synergistic development between advanced packaging and foundry services. He pointed out that CPUs, GPUs, and accelerators are merely components of an AI system. As models and clusters continue to scale, the bottlenecks will shift from individual chips to interconnects, power delivery, thermal management, packaging, and memory. He also made substantial early investments in companies such as Credo, Astera Labs, DustPhotonics, and Celestial AI, closely monitoring technological advancements in high-speed data center interconnects. Finally, he addressed a somewhat "back-to-roots" question: Will Intel re-enter the memory chip business? Lip-Bu Tan's answer was that new memory architectures are one of his "pet projects." There are many ways to stack CPUs and memory together, but the specific details are not yet ready to be disclosed.
Why is this considered a "back-to-roots" question? To understand this, we must trace back to Intel's inception. Intel actually started as a memory company. Founded in 1968, its earliest products included the 3101 SRAM and 1103 DRAM. It gradually exited the memory market due to the rise of Japanese manufacturers. In recent years, its last highly representative move was co-developing 3D XPoint with Micron and launching the Optane product line. However, this was ultimately discontinued in 2022 as the market scale fell short of expectations. Intel's SSD business has also gradually phased out over the past decade. Consumer-grade Optane 900P, enterprise-grade DC P5800X series, and hybrid solid-state drives like the H10 and H20 series have all faded from the mainstream spotlight.
Over the past two decades, memory has been viewed by the market as a commodity. However, driven by the demand for AI computing clusters, the prices of 3D NAND, DRAM, and HBM have surged, with gross margins reaching 90% or even higher. Samsung, SK hynix, Micron, and Kioxia have suddenly become extremely profitable companies. Lip-Bu Tan also told the media, "I used to always say, 'Don't invest in memory because it's a commodity,' but the situation is different now. There are many new technologies emerging. So, we are working on a project that I am personally quite focused on—some new memory architectures. I think you've seen the news: I hired my good friend Suk-hee Lee, who used to be the CEO of SK hynix. So, you probably have an idea of what I'm considering. We cannot disclose it at this moment." Although not explicitly stated, the implied meaning is clear. This marks the first time Intel's top management has spoken so directly about returning to the memory business. Furthermore, Intel's recruitment of Suk-hee Lee, the former CEO of SK hynix, is highly significant. During his tenure at SK hynix, he drove the development of high-end DRAM, continuously bet on HBM, and led the acquisition of Intel's NAND business. The author believes that Intel values his forward-looking judgment on industry trends even more. His expertise perfectly complements Intel's HBM and high-end DRAM efforts. In the future, Intel is highly likely to focus heavily on the ultra-dense stacked packaging of HBM memory and CPU chips.
XBM Patent Targets System-Level Packaging
Alongside the news of Intel's imminent return to memory, there is another technical update. The United States Patent and Trademark Office published a patent filed by Intel on July 2, 2026: US 2026/0191095 A1, titled "Ultra High Bandwidth Memory with Backend Transistors." The core concept of this patent is a novel High Bandwidth Memory (HBM) architecture plan designed to overcome the current packaging and cost bottlenecks of interposer-based HBM. The patent describes a technology named "cross-batch memory (XBM)": an ultra-high bandwidth memory with backend transistors. While maintaining the same dimensions as HBM4, it replaces traditional DRAM and its ultra-wide interfaces with backend (BEOL) transistors and Serial Universal Chiplet Interconnect Express (UCIe) links. Essentially, it is a memory stack that eliminates the expensive silicon interposer and reduces the package size, thereby solving the high assembly cost issue of traditional HBM memory, while also incorporating built-in defect repair capabilities.
Intel Patent Package Cross-Sectional View (Image source: Intel)
The patent document provides a detailed explanation of the stacking of this logic chip (106) and memory chip array (104). Each memory chip contains a DRAM circuit composed of a single transistor and single capacitor (1T1C) cell, manufactured using the back-end-of-line (BEOL) process. By leveraging Intel's expertise in logic circuit processes to replace part of the external DRAM supply, it then uses TSV "trench" interconnects (TSV trenches rather than traditional vertical interconnects) and double-sided HBI (Both-sided high-bandwidth interconnect, meaning both the top and bottom sides of each DRAM die can feature high-bandwidth interconnects) to stack multiple DRAM dies. Finally, data is output through the base die via a UCIe 32 GT/s interface.
In the patent, a single DRAM chip has a capacity of 1.5GB, comprising 768 blocks arranged in a 32x24 layout. It features 8 channels, each of which can be further divided into 8 sub-channels, totaling 64 sub-channels. Optional configurations include 8-layer stacking and up to 16-layer stacking, corresponding to capacities of 12GB to 24GB. Compared to HBM3e, this capacity is relatively small (a single HBM stack of 8/12 layers can typically achieve 24/36 GB). However, the primary advantage of this solution lies in interface standardization and the manufacturing of DRAM using logic chip processes.
Intel Patent Package Chip Stack Oblique View (Image source: Intel)
Regarding the interface, data is output via UCIe I/O bundles at a rate of 32 GT/s, adopting the standard interconnect protocol for Chiplets rather than the proprietary memory interface used in HBM. This implies that Intel intends to make this 3D DRAM stack a standard Chiplet, making it easier to integrate with CPUs, GPUs, and AI accelerators. Customers can directly connect to the DRAM stack using the more universal UCIe standard protocol. There is a strong trend of using logic processes and advanced packaging to manufacture Chiplet-based DRAM, which will naturally offer certain advantages in terms of cost and yield.
The industry is also paying close attention to another route taken by Intel. The Z-Angle Memory (ZAM), co-developed with SoftBank's subsidiary SAIMEMORY, has already been pushed toward commercialization. The innovation of ZAM lies in its hybrid bonding technology, adopting a "Via-in-One" architecture that stacks nine layers of DRAM together. The inter-layer silicon thickness is approximately 3um, enabling a bandwidth density that can achieve twice that of HBM4. Intel's XBM patent is filed exclusively by itself, whereas ZAM is jointly developed by two parties, presenting a strategy of walking on two legs.
It must be said that this patent provides the industry with a new perspective. Stacking DRAM can also adopt Chiplet standardization; UCIe is no longer just a die-to-die interconnect between CPUs and GPUs, as memory blocks can also be standardized and modularized. Meanwhile, the idea of manufacturing DRAM chips using logic chip processes is highly appealing. However, the performance and yield of BEOL DRAM, as well as the thermal management and cost of multi-layer TSV/HBI, remain formidable challenges.
Conclusion
As a veteran deeply rooted in the semiconductor industry for many years, Lip-Bu Tan brings extensive experience. From joining Intel in 2022 to becoming CEO in March 2025, Intel's development momentum has been formidable. At the end of this sharing session, he also mentioned that he is a long-termist himself. Whether participating in startups or running Cadence, he has always measured progress on a decade-long scale. For Intel, he will consider its development over the next ten or even fifteen years. This should also inspire domestic semiconductor companies: long-termism is perhaps the most core and fundamental principle that an industry should uphold.
The illustrations in this article are generated by generative AI.
References:
"Intel CEO hints at return to the memory business — says market is ripe for innovation, hints at stacking memory and CPU"
"Intel’s Next Big Bet? CEO Lip-Bu Tan Eyes Memory-CPU Stacking As Chip Shortage Deepens""Intel patent reveals new XBM memory architecture that ditches HBM's costly silicon interposer — backend-transistor DRAM stack uses UCIe links and built-in repair to ease AI's memory bottleneck"US 2026/0191095 A1 "Ultra High Bandwidth Memory with Backend Transistors"
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