Semiconductor Glass Substrates
Given the increasing size and soaring power consumption of AI (Artificial Intelligence) chips, traditional organic substrates begin to experience imperceptible warpage at high temperatures, while silicon interposers are constrained by high dicing costs. Finding a carrier for future ultra-large computing chips that is robust, flat, and capable of high-speed signal transmission has become an urgent challenge for the entire industry.
The answer points to a material we are all too familiar with in our daily lives—glass.
With its extremely high flatness, a coefficient of thermal expansion (CTE) close to that of silicon wafers, and excellent electrical insulation properties, glass substrates are transitioning from their traditional role in display manufacturing to become the next critical battleground in the field of advanced packaging.
Currently, from Samsung and SK Absolics to TSMC (Taiwan Semiconductor Manufacturing Company), global semiconductor and tech giants have rolled out their roadmaps. The race for capacity and technology surrounding next-generation packaging carriers is now in full swing.
On July 24, Intel and Lens Technology, a leader in precision manufacturing, signed a strategic cooperation memorandum, announcing a joint effort to tackle advanced packaging technologies based on glass substrates. This cross-industry collaboration between a semiconductor design giant and a glass processing leader not only breaks the boundaries of traditional supply chains but also accelerates the R&D and validation of glass substrates, adding a significant stroke to the global semiconductor industry's competition in foundational materials.
01. Intel Partners with Lens Technology to Accelerate Glass Substrate R&D
According to official announcements from both parties, this strategic collaboration focuses on the urgent demand for ultra-high-performance computing platforms in the AI era, aiming to jointly explore and accelerate the commercialization of advanced packaging solutions based on Through Glass Vias (TGV).
In terms of division of labor, the two parties have built a complementary closed loop of "design architecture" and "precision manufacturing." Intel will provide descriptive architecture information, Design for Manufacturability (DFM) guidelines, benchmarking, and validation systems.
Lens Technology, leveraging its accumulation in glass material research, high-precision laser micro-machining, and mass production, will lead the breakthroughs in key processes such as high-precision laser drilling, metallized via deposition, and multi-layer routing. In addition, the collaboration will extend to broader ecosystem areas such as AI PC components, data center cooling, and smart robot hardware.
Currently, this collaboration is in the stage of technology R&D and validation. Lens Technology has internally built a supporting pilot production line and is conducting sample trial production. Some samples have successfully passed the initial Proof of Concept (PoC) and officially entered the customer technical testing phase, but have not yet moved into large-scale commercial mass production.
02. A Decade of Layout: Intel's "Glass Marathon"
As the earliest semiconductor giant to bet on glass substrate technology, Intel has accumulated over a decade of R&D experience in this field. Long before traditional organic substrates could still meet the needs of mainstream chips, Intel's R&D team began exploring the foundational processes of glass interposers and glass core substrates in its packaging laboratory in Chandler, Arizona, USA.
The firm choice of glass substrates is due to their generational advantages in physical and electrical properties that are unmatched by traditional materials.
According to Intel's official performance statements, the interconnect density of glass substrates can be increased by up to 10 times, supporting smaller microbump pitches and denser transistor connections, making them extremely suitable for tightly integrating dozens of chiplets within a single package.
In terms of physical and thermal stability, the CTE of glass is highly close to that of silicon chips, and its surface flatness is extremely high. This can effectively suppress warpage in ultra-large packages, significantly improving chip packaging yield and reliability under high-power operation.
Furthermore, in terms of electrical transmission performance, the low dielectric constant and ultra-low loss characteristics of glass can significantly reduce power consumption in high-speed data transmission, greatly enhancing signal transmission rates and bandwidth density.
Strategically, Intel has been accelerating its commercialization pace in recent years. Previously, Intel successfully demonstrated glass substrate prototype samples in the laboratory, incorporating Co-Packaged Optics (CPO) technology and high-density chiplet interconnects.
To bridge the gap from R&D to mass production, Intel has designated its Rio Rancho facility in New Mexico, USA, as the world's first large-scale mass production base for glass substrates. According to Intel's plans, as cooperation with global supply chain partners like Lens Technology deepens, glass substrate technology is expected to gradually achieve pilot deployment and move towards full commercialization between 2026 and 2030.
03. Giants Bet Big: The World Enters the "Glass Era"
The collaboration between Intel and Lens Technology is just a microcosm of the current global semiconductor industry's race in the glass substrate track. Facing the exponential growth in computing power demand and the shortage of traditional silicon-based packaging capacity, semiconductor giants and upstream equipment and material suppliers in South Korea, Taiwan (China), Europe, and the US are comprehensively scaling up this technological route.
The South Korean supply chain is moving swiftly in capacity layout for glass substrates.
Absolics, a joint venture under SK Group, has established a glass substrate factory in Covington, Georgia, USA, and received financial support from the US CHIPS Act. Currently, the factory is still in the stage of equipment debugging, process optimization, and performance validation. It is expected to start production by the end of 2026 and has not yet entered the stage of large-scale mass production and sample delivery.
Meanwhile, Samsung Group is also making full efforts to integrate internal resources. The pilot production line built by Samsung Electro-Mechanics (SEMCO) in Sejong, South Korea, has entered efficient operation. They have successively collaborated with Japan's Sumitomo Chemical and Soulbrain to tackle challenges in raw materials and wet deep etching. Samsung Electronics plans to start pilot production in 2027 and achieve scale introduction in 2028, applying glass interposers to the packaging structures of high-end chips such as next-generation HBM4 (High Bandwidth Memory).
In terms of wafer foundry and packaging giants, TSMC is reshaping the competitive landscape with its unique Chip-on-Panel-System (CoPoS) route.
To solve the current problem of limited capacity and high costs of CoWoS silicon interposers, TSMC is actively trying to use square glass carriers/interposers to replace traditional round silicon interposers and organic substrates, assembling chips through ultra-large square glass panels of 250×250 mm or even 510×515 mm. This approach can not only increase panel area utilization to over 90% but also significantly reduce large-area dicing losses, becoming another key path to solving the packaging stress issues of ultra-large AI chips.
This technological revolution has also flowed upstream, deeply driving the upgrade of the upstream materials and precision equipment ecosystem. Glass material giants Corning and SCHOTT have successively launched ultra-thin glass substrates with high flatness and low CTE, specifically developed for semiconductor packaging.
In the most critical TGV processing link, precision equipment manufacturers such as Germany's LPKF, Japan's Tokyo Electron (TEL), and DISCO are working closely with upstream and downstream industry chains to develop high-throughput laser micro-drilling machines and high-speed electroplating via-filling equipment, striving to reduce the per-via processing cost by an order of magnitude.
On the downstream demand side, cloud computing and chip giants such as NVIDIA, AMD, Apple, Amazon Web Services (AWS), and Microsoft have all listed glass substrates as key evaluation options in their next-generation roadmaps. Cloud data centers are becoming the core application scenarios for the first wave of glass substrate explosions.
Looking back, from an ideal material in the laboratory to a mass production solution that truly drives production lines, glass substrates have encountered quite a few pitfalls along the way. High-density TGV drilling is prone to edge chipping, via filling is often uneven, and large-size handling is susceptible to cracking. These highly representative manufacturing challenges once deterred many manufacturers. However, with the evolution of laser micro-machining and novel etching processes, these former bottlenecks are being flattened one by one.
This handshake between Intel and Lens Technology provides a very clear signal to the industry: in the second half of advanced packaging, relying solely on chip design or material manufacturing is no longer sufficient to hold the fort. The deep binding between semiconductor giants and precision manufacturing leaders is becoming the new normal. As more and more industry chain players build the foundation of computing chips on glass, this cross-industry experiment in materials and processes may become the standard answer for next-generation high-performance computing faster than we imagine.
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