【Relevant Companies Mentioned in This Article】HT-Tech / Pangu Semiconductor, SJ Semiconductor, CXMT, XMC, SMIC, Fastprint, SCC / Sky Chip Interconnect, Zhejiang WAZAM New Materials, TSMC, PTI, ASE, Hsingchen Technology, JCET, TongFu Microelectronics, CR Micro / Sipan Micro, ECHINT Technology, Fozhixin Microelectronics, 3D CHIPS (GUANGDONG) Technology, Sky Semiconductor, WG Tech / TGVTECH, BOE, Lens Technology, Samsung Electro-Mechanics, Intel, Innolux, Absolics, Corning, SCHOTT, AGC, Rainbow Group, Triumph Science & Technology, Gebijia, Dongxu Optoelectronics, Naura Technology, ACM Research, YingSu Integration, Xinqi Micro-Equipment, Yuanzhuo Weina, Han's Laser Semiconductor, DR Laser, Delon Laser, Xpeedic, Empyrean Technology, etc.
I. The Dilemma of Missing Ingredients: Three Scarce Structural Components in AI Packaging and the Pressure on Domestic OSATs
In the current industrialization of domestic high-computing-power AI chips, the core bottleneck constraining actual delivery volume is increasingly concentrated on three scarce structural components in advanced packaging: HBM (High Bandwidth Memory), Silicon Interposers, and high-end ABF substrates (FC-BGA carriers). A standard high-performance AI accelerator card must interconnect compute dies (SoC/GPU) with multiple HBMs via a silicon interposer at micron-level density, then mount the entire assembly onto a large-size ABF substrate with 16 to 26+ layers. If any of these three structural components faces shortages or quota restrictions, the entire AI chip cannot be packaged and delivered.
In Q3 2026, SJ Semiconductor (SJ Semi), a leading domestic 2.5D silicon interposer packaging and testing firm, faced performance pressure and reduced utilization rates during its rapid expansion phase. This deeply reveals the real pain point facing the domestic packaging and testing industry: the bottleneck determining the actual output of domestic AI chip packaging lines lies in the local supply chain completeness rate for the three critical structural components—HBM, silicon interposers, and high-end ABF substrates. If upstream constraints due to overseas capacity locks, export controls, or local yield ramp-up cycles persist, downstream packaging plants—even those with advanced 2.5D/3D lines—face the severe dilemma of "having no rice to cook despite having a kitchen," struggling to offset massive equipment depreciation costs!
II. Demonstrative Breakthrough: The Essence of Huatian Pangu's Rise and the Principles of Zhurong BiPoS and Shennong CoHiS
Against this backdrop of "constraints imposed by three scarce structural components," the 24th China Semiconductor Packaging Testing Technology and Market Annual Conference (CSPT 2026), held in Nanjing from November 4 to 6, saw HT-Tech and its subsidiary Jiangsu Pangu Semiconductor publicly display, for the first time, a 510×515 mm fully automated Panel-Level Package (PLP-BGA) product. This triggered high attention across the industry and created a strong demonstrative effect.
1. Industrial Chain Significance of Huatian Pangu: Directly Addressing the Two Major Pain Points of "Silicon Interposers" and "High-Order ABF Substrates"
• Replacing full-size silicon interposers with "Local Silicon Bridges + RDL": Instead of consuming entire 12-inch pure silicon wafers processed with tens of thousands of TSVs, only tiny silicon bridges are embedded at the edges of chiplet interconnections (initial small batches even replace parts of traditional silicon interposers directly with multi-layer high-density panel-level RDLs), saving over 90% of silicon interposer wafer consumption;
• Area Utilization Exceeds 95%, Die Capacity per Panel is 2.64x that of a Wafer, Cost Per Unit Drops by 66%, Reducing Dependency on Underlying ABF Routing: Compared to a 300mm circular wafer (total area ~706.9 cm², effective utilization rate only 60%-65%), the 510×515 mm square carrier used by Pangu has a total area of 2,626.5 cm² (3.715 times that of a wafer), with an area usage rate exceeding 95%. The number of dies accommodated per single board reaches 2.64 times that of a 12-inch wafer (an increase of 1.64 times), reducing the packaging cost per unit by up to 66%. Simultaneously, the upper panel-level high-density RDL can directly share the fine routing burden of the underlying ABF substrate, significantly reducing dependence on ultra-high-end ABF substrates with 20+ layers;
• Direct Chip Interconnection via TGV Glass Core Substrates: Replacing silicon interposers and organic ABF cores, breaking free from overseas supply chain constraints at the fundamental material system level.
2. Analysis of Pangu Packaging Technology Principles: From Initial PLP-BGA to "Zhurong BiPoS" and Then to "Shennong CoHiS"
(1) Initial Small Batch Stage: 510×515 mm PLP-BGA Exhibited at the Nanjing Annual Conference (Glass Temporary Carrier + RDL Large Board 2.XD Structure)
The 510×515 mm PLP-BGA large board product exhibited at Booth B01 of the Nanjing Packaging and Testing Annual Conference (Figure 1 left) is the 2.XD chip structure made by Pangu in the initial stage using a 510×515 mm glass temporary carrier and pure RDL methods. In this stage (small batch in 2026), multi-layer high-density panel-level RDL replaces parts of traditional silicon interposers, achieving a single-board production capacity equivalent to 2.64 times that of a 12-inch wafer and reducing the packaging cost per unit by up to 66%.
(2) Advanced Panel-Level Silicon Bridge Stage: "Zhurong BiPoS (Bridge in Panel on Substrate)" Glass Temporary Carrier Manufacturing Route
The BiPoS (Zhurong: Bridge in Panel on Substrate, glass carrier manufacturing route) structure diagram published by Pangu in their presentation (see the purple box in Figure 2 left) displays the upper core structure after cutting from the 510×515 mm large board product—notably, the area enclosed by the purple box already integrates local silicon bridges (Bridge)!
Why might the first batch of 510×515 mm PLP-BGA physical products currently displayed not yet integrate silicon bridges, while integrating them necessitates the "Zhurong (BiPoS) glass carrier manufacturing route"? Precisely because silicon bridge solutions impose extremely stringent requirements on panel flatness, Coefficient of Thermal Expansion (CTE) matching, and warpage control. Traditional organic carriers or ordinary stainless steel carriers cannot control micron-level Die Shift during molding and curing, thus requiring high-rigidity, CTE-adjustable glass temporary carriers (Zhurong BiPoS) or future glass core substrates (Shennong CoHiS) to act as the "stabilizing anchor." Comparing with TSMC's actual six-step CoWoS-L process flow (① Prepare 300mm circular glass or silicon carrier wafer → ② Mount LSI small silicon bridges and vertical conductive copper pillars (TIV), inject EMC, and CMP polish into a 12-inch circular "Reconstituted Wafer" → ③ Perform multi-layer micron-level ultra-fine RDL redistribution on the circular reconstituted wafer → ④ Flip-chip mount GPU/SoC dies and multiple HBMs, filling underfill → ⑤ Dicing: Cut the 12-inch circular reconstituted wafer filled with chips and embedded silicon bridges into individual CoW modules → ⑥ Plant C4 solder balls at the bottom, finally mounting onto the lower ABF carrier), it is confirmed that the silicon bridges in Huatian Pangu's "Zhurong (BiPoS)" structure are indeed manufactured beforehand on the front-end panel-level process (510×515 mm glass temporary carrier). Its four-step coordination flow is: ① Borrow scaffolding (Apply photosensitive adhesive to510×515mm transparent glass temporary carrier) → ② Build on scaffolding (Route RDL on glass, embed silicon bridges, mount SoC and HBM, inject and cure) → ③ Remove scaffolding (UV laser penetrates glass to decompose photosensitive adhesive, completely peeling off and recycling the glass temporary carrier) → ④ Forming and Delivery (The remaining permanent base is singulated, planted with AB2 solder balls, and mounted onto the lower packaging substrate).
(3) Endgame Glass Core Substrate Stage: "Shennong CoHiS (Chip on Hybrid integrated Substrate)" No AB2 Soldering and "First Generation Divine Series"
Looking toward subsequent evolution, when the architecture upgrades to higher-order forms integrating silicon bridges, the more disruptive endgame direction is to directly integrate silicon bridges within the RDL structure of the TGV (Through-Glass Via) Glass Core Substrate during the RDL routing process—this is precisely the "Shennong CoHiS (Chip on Hybrid integrated Substrate)" architecture announced by Huatian Pangu (see Figure 3)!
After completing RDL routing and integrating silicon bridges on the surface of the TGV glass core substrate, "Shennong (CoHiS)" directly flip-chip interconnects single SoCs and HBM chips onto this fused glass substrate using micro-bumps—directly eliminating the AB2 solder ball layer between the upper panel-level RDL/Bridge structure and the lower substrate (no AB2 soldering), mounting chips directly onto the hybrid integrated glass core substrate with vertical vias! In the right image of Figure 3, showing Pangu's "First Generation Divine Series" layout: It features a large 5X (66×66 mm) TV size, Bump pitch of 40μm, RDL line width/space of 8/8μm, and uses a fused glass substrate. The green center represents 6 SoCs, the blue sides represent 12 HBMs, and the red strips spanning between SoCs and HBMs, as well as between SoC seams, are the silicon bridges pre-embedded in the glass core substrate's RDL layers!
III. Reticle Limit: Cutting Losses of 12-Inch Reconstituted Wafers and the Essence of Migration from Glass Carriers to Glass Panels
1. Reticle Limits Force Transition from Round to Square: Wafer Loss Occurs During Cutting of 12-Inch Circular Reconstituted Wafers (CoW)!
• SJ Semi Crosses 3.3x and 6x Reticle Thresholds: Officially released and mass-produced the SmartPoser®-Si 3D silicon interposer platform with a 3.3x reticle size (~2,830 mm²) on August 31, 2026; immediately followed by the release of the SmartPoser®-BD 2.5D local silicon bridge (Bridge Die) interconnection technology with a massive 6x reticle size (~5,148 mm²) on October 12, 2026, supporting super-large multi-chiplet packages exceeding 80×90 mm.
• Hubei Hsingchen Technology Focuses on 4x Reticle 2.5D/3D Heterogeneous Integration: Hubei Hsingchen Technology Co., Ltd., which has invested over 7 billion CNY in Phases I and II and recently completed a nearly 5 billion CNY Series A financing round, officially built and started operations of China's first 3D advanced packaging mass production line in Wuhan Optics Valley on September 30, 2026. The core focus is a high-performance 2.5D/3D heterogeneous integration platform combining 4x reticle (4x Reticle, ~3,432 mm²) with HBM and 3D TSVs.
• TSMC Sprinting Towards 5.5x and 14x Reticle Limits: TSMC's CoWoS-L (5.5x reticle) packaging area, mass-produced in 2026, has approached 4,700 mm², while the planned 14x reticle super-package for 2029 pushes the area to 12,000 mm², with a span exceeding 100mm.
It must be emphasized: Wafer loss does not occur on the bottom-most square ABF carrier, but during Step 5, when cutting the 12-inch (300mm) circular reconstituted wafer (CoW)! SJ Semi's 3.3x silicon interposer and 6x reticle silicon bridge, Hubei Hsingchen's 4x reticle, and TSMC's current CoWoS-L are primarily still manufactured on 12-inch (300mm) circular wafers.
When the reticle size expands to 6x (>5,100 mm²), only 5 to 8 units can be cut from a single 300mm disc; once evolving to 14x (12,000 mm²), only 1 to 2 effective modules can be obtained from a single disc, with more than half of the disc area becoming edge waste! Because super-large reticles hit physical and economic limits during singulation of circular reconstituted wafers, the industry is inevitably forced to transition to square panel-level packaging.
2. Truth Behind the Fate of Three Base Types and "UV Laser Penetration Debonding": The Essence of Migration from Wafer-Level Glass to Panel-Level Glass
• In Classic CoWoS-S—Pure Silicon Base (Silicon Interposer) Remains Forever at the Bottom of Chips: The thin gray middle layer is essentially a 12-inch pure silicon wafer processed with TSV vertical vias and multi-layer copper routing. On the production line, it is ground down from the standard thickness of 775μm to just 50-100μm. It is opaque and remains permanently sandwiched between the chip and the substrate after singulation.
• In CoWoS-L / SJ Semi SmartPoser®-BD / Huatian Zhurong BiPoS—Organic/Molded + Silicon Bridge Base Remains, Temporary Carrier Is Completely Peeled Off: The middle layer is a permanent composite base consisting of Epoxy Molding Compound (EMC) wrapping several small silicon bridges (Bridge) with multi-layer high-density organic copper routing (RDL) on the surface; however, the entire 12-inch disc (or 510×515 mm square panel) relied upon for their manufacture belongs to the "Temporary Carrier." After mounting the silicon bridges, RDL, and chips, it has been completely peeled off on the production line!
• In Future Glass Core Substrates (Glass Core Substrate, e.g., Huatian Shennong CoHiS)—Permanent TGV Glass Base Is Not Removed: Special functional glass drilled by laser and filled with copper pillars (TGV) serves directly as the permanent core layer base soldered onto the mainboard and is not removed.
Why do modern major manufacturers prefer "transparent high-borosilicate glass" over "silicon wafers" as temporary bases for CoWoS-L and panel-level fan-out reconstruction? Because silicon wafers are opaque and have extremely low debonding yields, whereas transparent high-borosilicate glass has a UV transmittance rate of over 90% for 308nm / 355nm ultraviolet lasers! By pre-coating a few hundred nanometers thick light-absorbing release layer (LTHC), cold UV laser scans from the back side of the glass during debonding (UV Laser Debonding). The glass does not heat up; the release layer instantly undergoes photochemical vaporization decomposition, allowing non-destructive peeling with zero mechanical stress at room temperature within tens of seconds, achieving a yield close to 100%. Moreover, the glass carriers can be recycled dozens or even hundreds of times after acid washing!
The Essence of Migration from "Wafer-Level Glass" to "Panel-Level Glass": For multi-reticle advanced packaging by TSMC, SJ Semi, and Hubei Hsingchen, the material and debonding processes of "glass temporary carrier + laser peeling" have long been maturely implemented at the underlying manufacturing level. The current bottleneck facing the industry is not that "glass carrier technology is unfeasible," but rather that "the 300mm circular geometric carrier has hit a physical wall." When fabricating 6X reticles (like SJ Semi SmartPoser®-BD) or 5.5X reticles (like TSMC CoWoS-L) on 300mm glass discs, expensive ultra-fine RDL and silicon bridges at the edges are forcibly cut away and discarded due to the arc shape, resulting in extremely high allocated costs per good interposer. Therefore, companies like Huatian Pangu deploying 510×515 mm panels directly reuse the mature Temporary Bonding and Debonding (TBDB) physical logic accumulated by TSMC and SJ Semi on 300mm circular glass carriers in terms of chemical material systems and peeling mechanisms. The core qualitative change lies in scaling and spreading this mature "glass temporary carrier manufacturing solution" from a wafer to a square panel with 3.7 times the area, completely resolving the economic dilemma of edge utilization for super-large reticle chips!
IV. Silicon Bridge Leadership: Full Panoramic Showdown of Four Major AI Panel-Level Packaging Platforms and Super-Large Reticle Solutions
In the wave of transitioning from 300mm circular glass temporary carriers to large square panels, large-area AI chip packaging in the coming years will continue to be led by "Local Silicon Bridges + Panel-Level High-Density RDL." Currently, the four most representative global AI/HPC panel-level packaging platforms are TSMC CoPoS, PTI PiFO, ASE FOCoS-Bridge, and Huatian Pangu HGemini® (Note: "Core Panel-Level Platform" and "Core Interconnection Topology" belong to two different dimensions):
1. TSMC CoPoS (Chip-on-Panel-on-Substrate): The Top Computing Commander of Panel-Level CoWoS-L/R
TSMC strictly locks the initial commercialization size of CoPoS at 310×310 mm (total area 961 cm², an improvement of over 85% compared to the effective arrangement area of a 300mm wafer). Its core interconnection topology translates CoWoS-L (organic RDL interposer embedding LSI local silicon bridges, supporting sub-1μm ultra-fine line widths) and CoWoS-R entirely onto a 310×310 mm square glass temporary carrier for reconstruction, reserving COUPE silicon photonics CPO interfaces at the edges. Equipment validation at the Caoyu Longtan plant in 2026, small-batch trial production in 2027, and large-scale mass production from late 2028 to 2029; the substrate route adopts a two-step approach: "2027–2028 rectangular glass temporary carrier → 2028–2029 permanent TGV glass core substrate."
2. PTI PiFO (Panel-in-Fan-Out): Pioneer of Panel-Level Embedded Silicon Bridges with Ten Years of Deep Cultivation and Yield Over 90%
PTI initiated the Bamboo Park Factory III project as early as 2016, building the world's first 510×515 mm fully automated FOPLP mass production line. The PiFO (Panel-Level Embedded Silicon Bridge) interconnection topology, designed specifically for AI/HPC, embeds local silicon bridges within the molding/dielectric layer of the 510×515 mm reconstituted panel, creating 2μm/2μm high-density copper RDL layers above. Current line yield has broken through 90% and is moving towards 98%. Capital expenditure doubled to NT$40 billion (~$1 billion USD invested in FOPLP) in 2026. Partnering with AMD and Broadcom (joint venture XCIP), volume ramp-up is expected in Q2 2027.
3. ASE Technology Holding FOCoS-Bridge (VIPack™ Platform): Chip-Last Test-Then-Mount and Dual-Size Track Parallelism
ASE focuses on panel-level FOCoS-Bridge under the VIPack™ platform: firmly adopting the Chip-Last (RDL-First, making RDL and silicon bridges first, then mounting chips) interconnection topology—pre-manufacturing 5-layer 2μm/2μm high-density fan-out RDL layers and embedding sBT local silicon bridges on square carriers, performing 100% electrical testing before mounting KGD computing dies, supporting super-large packages of 67×67 mm and above. The Kaohsiung plant pursues dual-track expansion with 310×310 mm (aligned with TSMC CoPoS specifications) and 600×600 mm sizes.
4. Huatian Pangu HGemini® and Domestic Super-Large Reticle Camp (SJ Semi, Hubei Hsingchen) Collaborative Breakthrough
Huatian Pangu's HGemini® platform locks onto the 510×515 mm large board specification (total investment 3 billion CNY, Phase I 1.5 billion CNY, annual output 86,400 boards), replacing silicon interposers and TSVs with panel-level multi-layer high-density RDL fan-outs (die capacity per board 2.64x, cost reduction 66%). Small-batch production starts in 2026, accelerating the leap along Zhurong BiPoS (glass temporary carrier silicon bridge) → Shennong CoHiS (2028 permanent TGV glass core substrate silicon bridge direct connection). Domestically, SJ Semi (3.3x reticle SmartPoser®-Si and 6x reticle SmartPoser®-BD local silicon bridge) and Hubei Hsingchen Technology (first 3D advanced packaging mass production line in Wuhan Optics Valley, focusing on 4x reticle 2.5D/3D heterogeneous platforms) are also advancing at full speed on super-large reticle silicon bridges and 3D integration.
V. Endgame Outlook: Permanent Glass Core Substrate RDL Silicon Bridge Direct Connection and Full Industry Chain Map of Glass-Based Technologies
1. Future Evolution Logic of AI Chip Packaging: RDL-Embedded Silicon Bridges on Permanent Glass Core Substrates Directly Connect SoCs and HBMs, Synergizing with 3D Stacking
Looking ahead to 2028–2030, the evolution of future AI high-computing chip packaging will inevitably move towards two ultimate directions: First, horizontally, using permanent Glass Core Substrates filled with vertical vias (TGV) as the base, creating RDLs on the glass core substrate surface and embedding local silicon bridges, then directly flip-chip interconnecting multiple SoCs and HBMs without AB2 solder balls (such as the Shennong CoHiS 6SoC+12HBM architecture); Second, vertically, deepening evolution towards 3D stacked packaging (such as SoIC logic+cache hybrid bonding stacking, XMC M-stacking bumpless wafer stacking, 12/16-layer HBM vertical stacking).
• Thoroughly Restructuring Packaging Layers (Eliminating AB2 Solder Balls, Three-in-One): After creating RDLs and embedding local silicon bridges on the surface of the permanent TGV glass core substrate, SoCs and HBMs are directly flip-chip soldered using micro-bumps. This simultaneously eliminates the "full TSV silicon interposer," the "20+ layer organic ABF core," and the "AB2 soldering layer" between the upper module and lower substrate found in traditional 2.5D packaging. The vertical interconnection path is shortened by more than half, thoroughly eliminating warpage risks associated with secondary reflow soldering;
• Physical Characteristics Deliver Dimensional Strike Against Organic Materials: Special glass core substrates possess nano-level surface flatness (perfectly adapting to sub-2-micron RDL lithography and high-precision silicon bridge embedding), extremely high Young's modulus, and a Coefficient of Thermal Expansion (CTE≈3 ppm/K) that precisely matches silicon wafers (2.6 ppm/K), fundamentally ending the warpage challenge for super-large spans exceeding 100mm;
• Supply Chain Security and Autonomous Control: Using special glass materials and TGV laser/electroplating processes, where China possesses rich capacity and processing foundations, to directly replace ABF films monopolized by Ajinomoto (over 95%) and restricted overseas high-order ABF substrates, building an independent and autonomous underlying material foundation for domestic AI chips.
2. List of Progress in Domestic and International Panel-Level Packaging (Temporary Carriers vs. Permanent Glass Core Substrates) and Full Glass-Based Industry Chain
Table 3: Classification Progress Table of Representative Companies in Domestic and International Panel-Level Packaging Platforms (Glass Temporary Carrier Route) and Permanent Glass Core Substrates (TGV Route)
3. Summary
Reflecting on this year's Nanjing Packaging and Testing Annual Conference, the strong breakout of Huatian Pangu's 510×515 mm panel-level packaging physical product was not merely an isolated single-process demonstration, but a landmark architectural breakthrough by China's semiconductor packaging and testing industry confronting the shortage crisis of the three core structural components: "HBM, silicon interposers, and high-end ABF substrates." In terms of technical inheritance, it directly reused the mature "glass temporary carrier + local silicon bridge + UV laser debonding (TBDB)" physical system verified by TSMC, SJ Semi, and Hubei Hsingchen on 300mm circular glass temporary carriers, expanding and spreading it to a 510×515 mm square large board (Zhurong BiPoS) with 3.7 times the area. This resolved the massive edge waste incurred during the dicing of 4x to 6x super-large reticles on 12-inch circular reconstituted wafers, saved over 90% of silicon interposer wafer consumption, achieved die capacity per board reaching 2.64 times that of a wafer, reduced packaging cost per unit by 66%, and shared underlying routing to reduce dependence on 20+ layer ultra-high-end ABF substrates. In terms of endgame evolution, with the accelerated implementation of the "Shennong (CoHiS)" permanent TGV glass core substrate route (such as the First Generation Divine Series 5x reticle 6SoC+12HBM fused glass substrate), directly integrating local silicon bridges within the glass core substrate RDL layer and eliminating AB2 solder balls to connect SoCs and 3D stacked HBMs, combined with the formation of a closed-loop full industry chain in China—from Rainbow/Triumph glass raw materials, Han's/DR/Delon laser modification, BOE/Lens/TGVTECH/3D CHIPS/Sky/Fozhixin TGV processing, JCET/TongFu/HT-Tech/Pangu/ECHINT/Sky packaging and testing integration, to Xpeedic/Silicon Core/Empyrean/UniVista EDA—China's AI computing chip advanced packaging is accelerating towards a new stage of full-chain synergy and scaled implementation.
References:
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