I. Project Analysis: Details of the CNY 3 Billion Phase II, Stage 2 Plan in Nanjing
On October 24, 2026, HT-Tech (002185.SZ), a leading domestic IC packaging and testing enterprise, explicitly responded to market concerns on the Shenzhen Stock Exchange investor interaction platform: The "HT Nanjing Integrated Circuit Advanced Packaging and Testing Industrial Base Phase II, Stage 2 Construction Project," invested with CNY 3 billion by its controlled subsidiary HT-Tech (Nanjing) Co., Ltd., has a construction period from June 2026 to May 2028 (Securities Star, Sina Finance).
Combining HT-Tech's previously disclosed board resolution announcements and project planning documents, the core engineering and financial parameters of this CNY 3 billion capacity expansion project are as follows (East Money, https://wap.eastmoney.com/a/202605223746946954.html):
· Location and Scale: The project is located in the Pukou Economic Development Zone, Nanjing City, Jiangsu Province. It relies on existing land within the current HT Nanjing plant for renovation and expansion, planning to build approximately 83,300 square meters of modern cleanroom facilities and supporting infrastructure.
· Equipment Procurement and Process Coverage: Focusing on the entire process of memory IC packaging and testing, the plan involves purchasing 2,772 sets of major production process equipment and testing instruments. Funding sources are self-raised by HT Nanjing.
· Capacity Targets and Economic Benefit Estimates: The construction period is 2 years (June 2026 to May 2028). After completion and commissioning, it is expected to package and test approximately 430 million units of memory ICs annually. Upon full capacity utilization, annual operating revenue is estimated at CNY 2.15 billion, with an annual net profit of CNY 126 million (East Money, Future Semiconductor).
· Target Downstream Application Markets: The project primarily targets high-density memory chip packaging and testing demands in fields such as AI computing power, servers (DDR5/enterprise-grade SSDs), data centers, automotive electronics, smartphones, and smart terminals. It directly supports the capacity expansion of top domestic memory manufacturers (such as YMTC, ChangXin Memory Technologies) and design companies.
II. Base Synergy: Matrix of Four Core Packaging and Testing Platforms in Pukou, Nanjing
The advancement of this CNY 3 billion Phase II, Stage 2 project is not an isolated capacity expansion but a key part of the "full-series advanced packaging and testing industrial cluster" that HT-Tech has been continuously building since settling in Pukou, Nanjing, in 2018. On the day before the interactive platform response (October 23, 2026), the construction of the No. 2 Factory Building Project of HT-Tech (Jiangsu) Co., Ltd., also located in Nanjing, officially commenced (Future Semiconductor, https://www.fsemi.tech/cms/xinwenkuaixun/5689.html).
A review of public investment records shows that HT-Tech has formed a collaborative operational landscape in Pukou, Nanjing, comprising four platforms: "HT Nanjing Phase I + HT Nanjing Phase II (including this CNY 3 billion memory-specific project) + HT Jiangsu (wafer-level) + Jiangsu Pangu (panel-level fan-out FOPLP)" (Ebang Semiconductor Network, Sina Finance):
1. HT Nanjing Phase I Project (Total Investment CNY 8 billion): Construction started in 2018, completed and commissioned in just 17 months. It focuses on FC-BGA, FC-CSP, BGA, and high-end memory packaging and testing. In 2025, HT Nanjing achieved operating revenue of CNY 3.787 billion and net profit of CNY 121 million, becoming a core pillar of the company's revenue growth.
2. HT Nanjing Phase II Project (Long-term Planned Total Investment CNY 10 billion, this Stage 2 investment CNY 3 billion): Based on the additional CNY 10 billion Phase II plan signed in March 2024, progress is being made steadily in stages. This CNY 3 billion Phase II, Stage 2 project (June 2026–May 2028) precisely targets high-end memory packaging and testing driven by AI computing power and servers. Upon reaching full capacity, HT Nanjing's annual revenue scale will jump from CNY 3.787 billion to nearly CNY 6 billion.
3. HT-Tech (Jiangsu) Wafer-Level Advanced Packaging and Testing Base (Planned Investment CNY 9.95 billion): Established in 2021, focusing on 12-inch wafer-level bumping, wafer-level fan-out (FOWLP), and silicon-based wafer-level packaging and testing. On October 23, 2026, its No. 2 factory building officially broke ground, further expanding mid-process wafer-level processing capacity.
4. Jiangsu Pangu Semiconductor Panel-Level Fan-Out Packaging (FOPLP) Project (Planned Total Investment CNY 3 billion): Controlled by HT Jiangsu, the first stage construction period is from 2024 to 2028. It plans to build approximately120,000 square meters of new floor area, specifically promoting the mass production of multi-chip high-density panel-level fan-out packaging (FOPLP). Upon full capacity, annual output value is expected to be no less than CNY 900 million (Ebang Semiconductor Network).
III. Technical Foundation: 3D Memory Stacking, 2.5D, and Panel-Level Fan-Out Packaging
HT-Tech has allocated all CNY 3 billion for the Nanjing Phase II, Stage 2 project to memory IC packaging and testing while simultaneously advancing the construction of Pangu Semiconductor and HT Jiangsu. This strategy relies on its technical accumulation in three key areas: high-density memory packaging, 2.5D heterogeneous integration, and panel-level fan-out packaging (FOPLP) (Sina Finance Annual Report Disclosure):
· High-Density 3D Memory Stacking Packaging Technology: For 3D NAND flash, LPDDR5/DDR5 DRAM, and enterprise-grade storage chips, HT-Tech has mastered the complete set of mass production processes, including ultra-thin wafer backside grinding and thinning, stealth dicing, ultra-thin DAF die attach film bonding, multi-layer stepped/interleaved chip stacking (8 to over 16 layers), ultra-fine pitch copper/gold wire bonding, and Molded Underfill (MUF), ensuring high-yield delivery capabilities.
· 2.5D/3D Heterogeneous Integration Platform (SiCS / eSinC / BiCS): Addressing the demand for co-packaging AI computing chips with HBM high-bandwidth memory, the company independently developed advanced packaging platforms such as SiCS (silicon bridge 2.5D heterogeneous integration), eSinC, and BiCS. These platforms achieve high-speed interconnection of multiple compute Chiplets through localized high-density silicon bridges or redistribution layer interposers. The stable yield rate of the existing 2.5D production line reaches 98.5% (OFweek, East Money Fortune Account).
· Multi-Chip High-Density Panel-Level Fan-Out Packaging (FOPLP): Relying on Jiangsu Pangu Semiconductor and the Kunshan base, the company uses large-size rectangular panels instead of traditional circular wafers for fan-out Redistribution Layer (RDL) processing, significantly improving unit area utilization and reducing per-chip packaging costs. Currently, panel-level packaging has entered the small-batch delivery stage, with preliminary research on TGV glass substrates and CPO co-packaged optics proceeding concurrently.
IV. National Landscape: Division of Labor Across Domestic and Overseas Bases and Consolidation of Huayi Microelectronics
From the perspective of the HT-Tech Group, the expansion of high-end memory and advanced packaging at the Nanjing base forms a clear gradient division of labor with the company's other five major production bases domestically and abroad, as well as recently acquired power device assets:
1. Operational Inflection Point in 2026 and Global Ranking Leap: Benefiting from the recovery of the memory industry cycle and capacity utilization rates exceeding 80%, HT-Tech achieved operating revenue of CNY 4.80 billion in Q1 2026 (+34.49% YoY) and net profit attributable to parent company shareholders of CNY 86.7864 million (+568.39% YoY). In the first half of 2026, the company realized packaging and testing revenue of approximately USD 1.52 billion, a 35.1% year-on-year increase. It surpassed Taiwan's PTI (USD 1.41 billion) for the first time among the global top ten OSATs, rising to fifth globally and third in mainland China. Comprehensive gross margin increased by 3.5 percentage points year-on-year to 14.3% (EEFocus, Caiwen Net).
2. Completion of 100% Equity Transfer of Huayi Microelectronics for CNY 2.996 billion, Completing the Power Device Landscape: On October 20, 2026, HT-Tech formally completed the industrial and commercial change registration procedures for acquiring 100% shares of Huayi Microelectronics (transaction consideration CNY 2.996 billion). Huayi Microelectronics specializes in the R&D, design, and packaging/testing of power devices such as 20V–150V medium-low voltage MOSFETs. After consolidation, it will deeply synergize with the Xi'an automotive-grade base, enhancing the company's main business profits (Future Semiconductor).
V. Industry Comparison: Differentiated Positioning and Progress of Three Major Domestic Packaging and Testing Enterprises
Placing HT-Tech's CNY 3 billion Nanjing project within the overall capacity expansion context of the three major domestic packaging and testing leaders (JCET, Tongfu Microelectronics, HT-Tech) in 2026 allows for an objective view of their differentiated strategic paths and potential risks (OFweek, East Money Fortune Account):
Comprehensive assessment indicates that HT-Tech's advancement of the CNY 3 billion Nanjing Phase II, Stage 2 advanced packaging and testing project holds the following three aspects of objective industrial significance and observation points:
1. Capturing the Certainty Dividend of Domestic Memory Expansion: Unlike JCET's heavy investment in AI computing power in Jiangyin/Lingang or Tongfu Microelectronics' deep binding with AMD, HT-Tech precisely anchors the "entire process of memory chip packaging and testing (annual production of 430 million units)" in Nanjing Phase II, Stage 2. It directly undertakes the outsourced incremental volume from the capacity expansion of two major domestic memory manufacturers and AI server DDR5/enterprise-grade SSDs, avoiding homogeneous internal competition (East Money, East Money Fortune Account).
2. Driving Demand for Procurement of 2,772 Sets of Packaging, Testing, and Wafer-Level Equipment: The phased procurement of 2,772 sets of equipment for Nanjing Phase II, Stage 2, combined with the groundbreaking of HT Jiangsu's No. 2 factory and the construction of Pangu Semiconductor's FOPLP production line, will provide sustained order increments for local equipment suppliers such as Xinyichang (die bonding), Chihi Microequipment (panel-level direct-write lithography), Naura Technology/Piotech (bonding/thin film), AMEC (etching), as well as Changchuan Technology and AccoTest (memory and computing test machines) during the construction period from June 2026 to May 2028 (Future Semiconductor, Ebang Semiconductor Network).
3. Objectively Examining Depreciation Pressure and Main Business Profit Realization Pace: It is necessary to rationally recognize that there is a two-year construction cycle for the CNY 3 billion Nanjing Phase II project from groundbreaking in June 2026 to commissioning in May 2028. During this period, substantial capital expenditures will gradually increase fixed asset depreciation and financial expenses. Meanwhile, the sustainability of its valuation repair will highly depend on the improvement strength of non-recurring adjusted net profit in subsequent quarters, the progress of head customer adoption for FOPLP panel-level packaging and 2.5D production lines, and the continuity of the memory packaging and testing price cycle (ZAKER Finance, East Money Fortune Account).
References:
1. Securities Star, "HT-Tech Responds to Semiconductor Packaging and Testing Topics on October 24: Nanjing CNY 3 Billion Packaging and Testing Project Expected to Start Production in May 2028", Securities Star / SZSE Interactive Easy, 2026-10-24. https://stock.stockstar.com/RB2026102500001062.shtml
2. Sina Finance Board Secretary Q&A, "HT-Tech: Subsidiary Invests CNY 3 Billion to Build Advanced Packaging and Testing Industrial Base Project (Construction Period June 2026 to May 2028)", Sina Finance, 2026-10-24. https://finance.sina.cn/stock/relnews/dongmiqa/2026-10-24/detail-iniwicvs1353645.d.html
3. China Securities Journal · CS.com.cn (Author Shen Nan), "HT-Tech: Plans to Invest CNY 3 Billion to Build Nanjing Integrated Circuit Advanced Packaging and Testing Base, Annual Operating Revenue Expected to Exceed CNY 2.1 Billion", East Money / China Securities Journal, 2026-05-22. https://wap.eastmoney.com/a/202605223746946954.html