From HBM4 Mass Production and HBM4E Competition to Advanced Packaging: Memory Power in the AI Computing Era
The information in this article is current as of July 2026. HBM product qualifications, capacity allocation, and customer market shares are changing rapidly. There may be a time lag between supplier announcements, research institute statistics, and actual customer adoption.
Over the past three years, the GPU has been the most closely watched hardware in the AI (Artificial Intelligence) industry.
However, if an AI acceleration system is broken down, the computing core is not the only determinant of its actual performance. The GPU needs to continuously read model weights, intermediate results, and KV Cache from memory; once the data supply speed cannot keep up, the expensive computing units will be left waiting.
This is the so-called "memory wall."
HBM (High Bandwidth Memory) is precisely the key technology to solve this problem. By vertically stacking multiple layers of DRAM chips, expanding parallel data interfaces, and placing the memory close to the computing chip, it significantly increases bandwidth and reduces the energy consumption of data movement.
Entering 2026, the HBM industry has moved from the volume ramp-up of HBM3E to the commercialization of HBM4 and customer qualification of HBM4E. Samsung and Micron have announced commercial shipments or mass production of HBM4, while SK hynix has also completed HBM4 product readiness and provided 12-layer HBM4E samples to major customers in June 2026. The HBM4E speeds disclosed by Samsung and SK hynix both reach up to 16Gbps, with a single stack bandwidth of approximately 4TB/s.
This means HBM is no longer a peripheral supporting product for AI chips, but is becoming a strategic component that determines GPU performance, system power consumption, product delivery, and the capital efficiency of cloud providers.
However, investors need to remain restrained:
HBM possesses genuine structural demand and high barriers, yet it has not detached itself from the capital cycle of the memory industry.
High demand does not necessarily mean permanent shortage, and high technical barriers do not necessarily mean permanent high profits.
I. Core Judgments: HBM Enters an Industrial Expansion Phase, Not a Mature and Stable Phase
The current HBM industry can be summarized by four judgments.
First, Demand Is Not Fabricated
The new generation of AI platforms has been deployed at scale around HBM4. In March 2026, NVIDIA announced that the Vera Rubin platform has entered full-scale production, and further stated at the end of May that related systems are being ramped up by the global supply chain. Micron's 36GB, 12-layer HBM4 has been shipped in mass production for Vera Rubin, and Samsung has also indicated that its HBM4 is used for the Vera Rubin platform.
Second, HBM4 Is Not a Simple Product Upgrade, But a Reconstruction of the Industrial Chain
HBM4 expands the I/O interface from 1024 bits in HBM3E to 2048 bits and begins to widely adopt logic Base Dies. Collaboration among memory manufacturers, wafer foundries, GPU vendors, and Advanced Packaging houses has further deepened, making products increasingly close to customized system components. Micron's HBM4 single stack bandwidth exceeds 2.8TB/s; Samsung's product sustains a speed of 11.7Gbps and has room for further improvement to 13Gbps.
Third, the Competitive Landscape Is Not Completely Solidified
SK hynix has gained a first-mover advantage with HBM3 and HBM3E, but HBM4 adds variables such as the logic Base Die, interfaces, thermal management, and customer customization, creating a window for Samsung and Micron to redistribute market shares. Tracking by TrendForce in June 2026 suggests that Samsung has gained an advantage in the HBM4 qualification and shipment progress for specific customers, while some of SK hynix's projects have experienced schedule adjustments.
Suppliers' announcements of "completion of development" and "readiness for mass production" do not carry the exact same meaning as "completion of qualification for specific customers" and "actual volume ramp-up" cited by research institutions.
Fourth, HBM Profit Margins Will Not Always Remain Higher Than Conventional DRAM
HBM commands high selling prices and high technical barriers, but it involves larger die areas, lower yields, longer manufacturing cycles, and additional costs for TSV, stacking, and testing. More importantly, HBM is typically priced under annual or long-term contracts, whereas conventional DDR5 prices can more quickly reflect spot shortages.
TrendForce estimates that, driven by the sharp rise in server DDR5 prices, the per-wafer revenue and profitability of 64GB DDR5 RDIMMs in the first quarter of 2026 once exceeded that of HBM.
This breaks a common misconception:
HBM is a high-value product, but this does not mean that HBM of any generation at any time is necessarily more profitable than conventional DRAM.
II. Why Conventional DRAM Cannot Meet the Needs of AI Chips?
A single GPU may possess tens of thousands of computing units.
As computing power increases, the system needs to read a massive amount of model parameters in an extremely short time. Conventional DDR memory is primarily mounted on the PCB (Printed Circuit Board) and connected to the processor via a relatively narrow data bus. Even if the speed of a single pin is steadily improving, bandwidth growth still tends to lag behind GPU computing power growth.
HBM adopts a different route.
Instead of primarily relying on increasing the ultimate speed of a single pin, it moves data simultaneously through a massive number of parallel I/Os.
The two approaches can be analogized as follows:
DDR steadily increases the "speed on a single-lane road";
HBM directly expands the road from dozens of lanes to thousands of lanes.
Multiple layers of DRAM dies are vertically interconnected via TSVs and then co-packaged with the GPU or AI ASIC on an interposer. The signal transmission distance is shortened, the number of interfaces increases, and the energy consumption per bit transmitted accordingly decreases.
| Product Generation | Typical Interface Width | Single Stack Bandwidth | Main Industry Phase |
|---|---|---|---|
| HBM3 | 1024 bits | Hundreds of GB/s | Early volume ramp-up for AI training |
| HBM3E | 1024 bits | Approx. 1.2TB/s and above | Current mainstream product |
| HBM4 | 2048 bits | Over 2.8TB/s | Commercialization in 2026 |
| HBM4E | 2048 bits | Approx. 4TB/s | Customer sampling and qualification |
SK hynix disclosed that the currently widely deployed HBM3E has a single stack bandwidth of approximately 1.2TB/s; HBM4 significantly increases bandwidth and improves energy efficiency by expanding the number of I/Os from 1024 to 2048. Both Samsung and SK hynix have pushed the single-pin speed of their HBM4E samples to 16Gbps.
However, increasing bandwidth does not come without a cost.
Wider interfaces require more connection points, more complex Base Die and interposer routing, and also increase the difficulty of controlling signal integrity, power delivery, thermal management, and packaging yield.
Every generational upgrade of HBM simultaneously raises the performance ceiling and the manufacturing threshold.
III. How Is a Single HBM Manufactured?
HBM is not a single IC (Integrated Circuit), but a highly complex integrated system.
It must go through at least five core stages.
1. DRAM Wafer Manufacturing
Samsung, SK hynix, and Micron first produce DRAM dies specifically for HBM.
HBM dies share some DRAM technology with conventional DDR chips, but differ in layout, interfaces, TSV structures, power consumption, and testing requirements. Because vertical interconnect areas need to be reserved, HBM dies are generally larger, and fewer chips can be diced from the same wafer.
2. TSV Vertical Vias
TSVs are vertical conductive channels manufactured inside the silicon wafer, enabling the transmission of data, power, and control signals between different DRAM layers.
This step involves deep silicon etching, insulating layers, metal filling, wafer thinning, and backside processes. Hole consistency, metal voids, and stress can all affect reliability and yield.
3. Wafer Thinning and Die Stacking
DRAM dies need to be thinned before stacking.
As products evolve from 8 layers to 12 and 16 layers, the control of single-layer thickness, overall height, warpage, and mechanical strength becomes more difficult. A defect in any single layer can lead to the scrapping of the entire HBM stack.
Therefore, HBM emphasizes KGD (Known Good Die), which is to identify "Known Good Dies" as much as possible before stacking.
4. Bonding and Underfill
Different manufacturers adopt different process routes.
SK hynix's representative solution is MR-MUF, which fixes the stacked structure through molded underfill material. Its HBM4E adopts an improved MR-MUF, which the company claims reduces thermal resistance by 17%. Samsung, on the other hand, continues to develop thermocompression bonding while simultaneously demonstrating hybrid copper bonding technology for products with 16 layers and above.
As the number of layers continues to increase, the pitch of traditional microbumps will approach its limit, and the importance of hybrid bonding may steadily increase.
5. Advanced Packaging with GPU
The stacked HBM cannot work independently; it needs to be connected with the GPU, AI ASIC, or related computing chips.
TSMC (Taiwan Semiconductor Manufacturing Company) CoWoS is currently a representative 2.5D packaging platform. It integrates computing chips and multiple HBM stacks within the same package through a silicon interposer or RDL interposer. TSMC disclosed that CoWoS-S can currently support an interposer of approximately 3.3 times the reticle size; larger packages can utilize CoWoS-L or CoWoS-R.
By 2028, TSMC plans to introduce a CoWoS with approximately 14 times the reticle size, which can integrate about 10 large computing dies and 20 HBM stacks.
This reflects a clear roadmap for AI systems:
The performance upgrade of a single chip is shifting towards co-scaling with multiple computing dies, multiple HBMs, and Advanced Packaging.
IV. Why Is It So Difficult to Expand HBM Capacity?
The supply constraint of HBM is not just because fab construction takes time.
It is simultaneously constrained by six types of capacity: front-end wafers, TSV, stacking, testing, Base Die, and Advanced Packaging.
TrendForce previously calculated that, under the same process node and capacity, the HBM die area is typically 35% to 45% larger than DDR5; the yield after TSV packaging may be 20 to 30 percentage points lower, and the production cycle is about 1.5 to 2 months longer.
SK hynix also explained that because the TSV structure expands the die area, HBM of the same capacity yields fewer effective dies from a single wafer, thus requiring more wafer input than conventional DRAM; it then has to undergo complex stacking and packaging.
This creates a significant supply crowding-out effect.
When memory manufacturers increase HBM production, they do not create new capacity out of thin air, but may occupy advanced DRAM wafer resources originally used for producing DDR5, LPDDR5X, and other products. The rise in HBM demand may instead cause the supply of conventional server and mobile DRAM to tighten.
Therefore, the HBM boom will increase memory manufacturers' profits through two paths:
First, directly selling high-priced HBM;
Second, squeezing the supply of conventional DRAM, thereby improving the market prices across the entire DRAM industry.
However, this mechanism can also work in reverse.
If the price of conventional DDR5 rises faster, memory manufacturers will re-evaluate the per-wafer revenue of different products and decide whether to allocate capacity to HBM or server DDR5.
This is also why analyzing HBM cannot solely focus on end-market demand; it is also necessary to study the wafer opportunity cost.
V. Why Is HBM4 a Watershed in Industrial Competition?
The core competition in the HBM3E era mainly focused on DRAM processes, stacking layers, thermal management, packaging yield, and customer qualification.
HBM4 introduces a more critical variable: the logic Base Die.
The Base Die is located at the bottom of the HBM stack, responsible for data interfaces, control, and signal connections. Past Base Dies had relatively simple functions, whereas HBM4 begins to adopt more advanced logic processes, enabling it to take on more interface and management functions.
Samsung's HBM4 adopts a 4nm logic Base Die; Micron's HBM4 expands the interface to 2048 bits. TSMC publicly offers N12 and N3 logic Base Die solutions for HBM4.
This change brings three impacts.
First, Wafer Foundry Enters the Core Value Chain of HBM
HBM is no longer entirely determined by the memory manufacturers' internal processes. Advanced logic Base Dies may be outsourced to wafer foundries for production, and the cost and delivery of HBM will also be affected by the capacity of logic processes.
Second, HBM Begins to Have Room for Customization
Different GPU and ASIC customers may have different requirements for interfaces, power management, error correction, monitoring, and data paths.
HBM products will gradually shift from relatively standardized memory to a "standard DRAM stack + customer-customized logic base."
Third, Customer Relationships Become More Critical
Products need to be co-defined in the early stages of chip design. Waiting until the GPU design is completed before seeking an HBM supplier may already be too late.
In July 2026, NVIDIA and SK Group further expanded their cooperation, with both parties planning to establish a long-term supply and co-development relationship around next-generation AI memory, including HBM.
This indicates that the core assets of future HBM suppliers are not just manufacturing technology, but also include:
The ability to enter customer roadmaps in advance;
The ability to co-design with GPU and ASIC vendors;
The ability to forecast customers' future volumes and specifications;
The ability to deliver millions of consistent products on time.
VI. Samsung, SK hynix, and Micron: How Will the Triopoly Landscape Change?
SK hynix: First-Mover Advantage Remains Deep
SK hynix has established strong customer relationships, stacking processes, and mass production experience during the HBM3 and HBM3E phases. The company announced the completion of HBM4 development and readiness for mass production in September 2025, and provided HBM4E samples in June 2026.
Its advantages mainly include:
Multi-generational HBM mass production data;
MR-MUF stacking and thermal management capabilities;
Joint development with core AI chip customers;
High market recognition and qualification foundation.
Its challenge is: the leader needs to simultaneously ensure new-generation performance, yield, and large-scale delivery; any qualification delay will provide a window for competitors.
Samsung: Vertical Integration Capabilities Regain Effectiveness
Samsung possesses DRAM, logic wafer foundry, Advanced Packaging, and large-scale manufacturing capabilities simultaneously.
In February 2026, Samsung announced the start of mass production and commercial shipments of HBM4; at the end of May, it began providing HBM4E samples to major customers. Samsung expects its HBM sales in 2026 to more than triple compared to 2025.
Samsung's potential advantages lie in:
Proprietary DRAM processes;
Proprietary 4nm logic Base Die;
Proprietary Advanced Packaging capabilities;
Being one of the world's largest comprehensive memory capacities.
If the synergy among various links goes smoothly, vertical integration can shorten cycles; however, when processes, packaging, and customer qualification encounter problems simultaneously, a complex organization may also reduce response speed.
Micron: Competing for Shares with Advanced Processes and Energy Efficiency
Micron's 36GB, 12-layer HBM4 began mass production shipments in the first quarter of 2026, with a single stack bandwidth exceeding 2.8TB/s, a 2.3x increase over its HBM3E bandwidth, and an energy efficiency improvement of over 20%. The company has also provided customers with 48GB, 16-layer HBM4 samples.
Micron's advantages are:
Advanced DRAM nodes;
Strong power consumption and performance competitiveness;
U.S. domestic supply chain identity;
Direct collaboration with GPU customers.
Its constraint is that the overall DRAM capacity scale is relatively limited, requiring strict wafer allocation among products like HBM, DDR5, and LPDDR.
Competition Conclusion
The HBM market in 2026 remains dominated by the three players, but their relative positions may shift with each generation of customer qualifications.
Unlike conventional DDR, HBM products cannot be quickly sold to a large number of customers once completed. The qualification progress of a major GPU platform can affect the supplier's market share, product mix, and profit margin for that year.
Therefore, when studying the HBM competitive landscape, one cannot solely look at the previous year's market share, but should focus on observing:
Next-generation customer qualification, actual procurement shares, and mass production yields.
VII. Where Is the Real Profit Pool of HBM?
The HBM industrial chain is long, but profits are not evenly distributed.
1. DRAM Manufacturers: Mastering Product Definition and Core Yield
Samsung, SK hynix, and Micron possess DRAM design, front-end processes, stacking, and customer qualification capabilities, making them the primary value capturers currently.
Their barriers stem from long-term manufacturing data, rather than a single piece of equipment or a single patent.
2. GPU and ASIC Vendors: Holding Ultimate System Pricing Power
HBM improves AI chip performance, but the value of HBM is ultimately delivered to customers through GPUs or AI servers.
GPU and ASIC vendors that master the software ecosystem, platform standards, and customer needs can typically obtain stronger system-level profits. Although HBM suppliers are important, they still need to meet the price, performance, and delivery requirements of platform customers.
3. Wafer Foundry: HBM4 Base Die Opens Up New Incremental Growth
The more complex the logic Base Die, the more important the position of advanced wafer foundries in the HBM value chain.
With the future development of customized HBM, the Base Die may integrate more customer-specific functions, further increasing its value and technical barriers.
4. Advanced Packaging: Shifting from Capacity Bottleneck to System Platform
Technologies like CoWoS are not just processing steps, but core platforms that determine how many computing dies and HBMs a package can integrate, whether signals can be transmitted stably, and whether the system can dissipate heat.
As packaging area and the number of HBMs increase, the value of Advanced Packaging is expected to steadily increase.
5. Equipment and Materials: Benefiting but with Obvious Divergence
Potential beneficiary directions include:
TSV deep silicon etching and metal deposition equipment;
Wafer thinning, dicing, and cleaning equipment;
Bonding and hybrid bonding equipment;
High-precision inspection and testing equipment;
Underfill, molding, and temporary bonding materials;
Interposers, substrates, and high-end packaging substrates.
However, "entering the HBM industrial chain" does not equal possessing high barriers.
Only enterprises that enter core processes, obtain major customer qualifications, and can follow product upgrades from 8 layers to 12 and 16 layers possess long-term value capture capabilities.
VIII. Why May High HBM Gross Margins Not Be Sustained in the Long Term?
HBM seems to possess an ideal business model:
Rapidly growing demand;
Only three suppliers;
Customers locking in capacity in advance;
Long product qualification cycles;
GPUs cannot be delivered without HBM.
But there are still three factors that will compress profits.
First, Manufacturing Costs Rise Significantly with Generations
HBM4 requires more advanced DRAM dies, more complex Base Dies, wider interfaces, and stricter packaging. HBM4E further increases speed and thermal management requirements.
Even if selling prices rise, costs may also rise synchronously.
Second, Annual Pricing Has a Lag
HBM contracts are generally signed early. Contracts help secure demand but may prevent suppliers from immediately enjoying spot market price increases.
Since the second half of 2025, conventional DRAM prices have risen rapidly, while some HBM contract prices were already determined in advance, causing HBM per-wafer profitability to be temporarily lower than that of high-capacity server DDR5.
Third, Customers Will Push for a Multi-Supplier Strategy
For GPU and cloud providers, a single supplier means delivery risk.
Once Samsung, SK hynix, and Micron all have available products, customers will improve security and enhance price negotiation power through multi-supplier qualifications. TrendForce expects that NVIDIA's HBM4 supply chain will gradually form a structure involving all three suppliers.
Therefore, the long-term return of HBM depends on:
Whether the selling price premium can continuously cover larger dies, lower yields, more complex packaging, and higher R&D costs.
One cannot just compare the selling price per GB, but must compare the return per wafer, per qualified stack, and all capital investments.
IX. Will AI Agents Further Drive HBM Demand?
Agents may become a crucial driver of HBM demand in the next phase.
Traditional chat models typically complete a single input and output, whereas Agents require continuous planning, tool invocation, data reading, action execution, and re-reasoning. A single user task may trigger multiple rounds of model invocations.
This will increase:
The number of inference tokens;
Long-context computation;
KV Cache occupation;
Concurrent requests;
Data movement of model weights and intermediate states.
NVIDIA stated that the Vera Rubin platform can provide 10 times the Agent throughput compared to Grace Blackwell in large-scale systems.
However, "the growth in the number of Agents" cannot be directly equated to "proportional growth in HBM demand."
Model quantization, sparsification, distillation, KV Cache compression, speculative decoding, and more efficient scheduling systems may all reduce the bandwidth or capacity required per unit task.
HBM demand can be simplified to:
Accelerator shipments × Number of HBMs configured per accelerator × Single stack capacity × Inventory buffer coefficient.
Any of these factors may change.
If the speed of model efficiency improvement outpaces task growth, the HBM demand corresponding to unit business revenue may decline; if the decrease in inference costs induces more usage, the Jevons Paradox may occur, and total demand may instead increase.
The most difficult thing to predict currently is not HBM technology, but exactly how much payable inference demand will be generated after the commercialization of AI applications.
X. What Does China's HBM Industry Really Need to Make Up For?
HBM is not a product that can be formed simply by stacking after obtaining DRAM chips.
A complete set of capabilities includes:
Advanced DRAM design and mass production;
TSV wafer processes;
Wafer thinning and high-layer stacking;
High-yield bonding and underfill;
Logic Base Die;
2.5D Advanced Packaging;
High-speed testing and failure analysis;
Joint qualification with GPU or AI ASIC customers.
A deficiency in any link will affect the final delivery.
The opportunities for China's HBM industry do not only exist in the final memory products.
Before the large-scale commercialization of complete HBM products, areas more likely to realize value realization first include:
TSV etching, deposition, and cleaning equipment;
Wafer thinning and temporary bonding materials;
Stacking, bonding, and inspection equipment;
High-end packaging substrates and interposers;
High-speed testers, probe cards, and interface solutions;
Thermal management and heat dissipation materials;
Customized Base Die and related IP.
However, domestic substitution cannot take "completion of qualification" as the only endpoint.
HBM product upgrade speed is very fast. Once a piece of equipment enters the HBM3E process, if it cannot continue to support HBM4's finer pitch, higher layer count, and stricter yield, its revenue and competitiveness may still decline rapidly.
The true barrier of the local supply chain is co-iteration with customers, rather than one-time substitution.
XI. Will There Be a Capacity Bubble in HBM?
This possibility exists, but the pace may be slower than conventional DRAM.
HBM supply growth is constrained by multiple links:
Advanced DRAM wafers;
TSV capacity;
Stacking equipment;
Yield ramp-up;
Logic Base Die;
Advanced Packaging such as CoWoS;
Customer qualification.
These constraints make it unlikely to experience disorderly capacity expansion in the short term.
However, supply will not be permanently constrained. Samsung, SK hynix, and Micron are all expanding HBM and related capacities, and TSMC is also continuously expanding the scale of the CoWoS platform. TrendForce expects that the proportion of DRAM wafer input used for HBM by the three major manufacturers will still steadily increase.
The potential capital cycle of HBM is:
GPU shortage and high profits
→ Customers lock in HBM in advance
→ Memory manufacturers expand wafer and TSV capacity
→ Packaging houses expand CoWoS and stacking capabilities
→ Customer inventory increases
→ AI chip or model roadmap changes
→ HBM supply and demand shift from shortage to looseness.
TrendForce already warned in early 2026 that delays in some AI chip upgrades and customer inventory accumulation may cause HBM supply and demand to gradually converge.
Therefore, what currently exists is not a "fake demand bubble," but more likely:
The risk of excessive capital investment driven by real demand.
Demand can grow genuinely, but if supply grows even faster, prices and profits will still decline.
XII. Three Industry Scenarios
Optimistic Scenario: HBM Maintains Long-Term Structural Shortage
AI training, inference, and Agent applications continue to grow rapidly, and shipments of GPUs and self-developed ASICs keep increasing.
The yield ramp-up of HBM4 and HBM4E is slow, and Advanced Packaging and Base Dies constitute long-term supply constraints. Long-term supply contracts maintain high prices, and the three major memory manufacturers maintain high profitability.
Under this scenario, the most valuable links are:
Leading HBM manufacturers;
Advanced Packaging platforms;
Logic Base Die foundry;
Core stacking, bonding, and testing equipment.
Neutral Scenario: Scale Growth, But Profit Margins Gradually Normalize
HBM demand maintains growth, and suppliers and packaging houses also expand capacity as planned.
Products shift from HBM3E to HBM4 and HBM4E, and the market size continues to expand, but multi-supplier competition and yield improvements cause unit prices to steadily decline.
Leaders remain profitable, but industry returns shift from shortage premiums to competition in technology, cost, and customer market share.
This is currently the more worthy scenario to serve as a baseline.
Pessimistic Scenario: AI Investment Slowdown Overlaid with New Capacity Release
If cloud providers' AI revenue cannot cover continuously increasing capital expenditures, the speed of GPU orders and data center construction may slow down.
Meanwhile, new capacities for HBM, TSV, and CoWoS begin to be released in a concentrated manner, customer inventory remains high, and HBM prices and capacity utilization rate decline.
Due to the high degree of specialization of HBM equipment and production lines, suppliers may face depreciation pressure, inventory losses, and declining capital returns.
XIII. When Studying the HBM Industry, Ten Indicators Should Be Continuously Tracked
First, actual shipments of major GPU and ASIC platforms.
Not how many products are announced, but how many accelerators customers actually deploy.
Second, HBM capacity and number of stacks configured per accelerator.
This determines the HBM value corresponding to a single chip.
Third, HBM4 and HBM4E customer qualification progress.
Sampling, qualification, mass production readiness, and commercial shipments need to be strictly distinguished.
Fourth, HBM product yield.
Yield is the core of profit margins and delivery capabilities, but public information is usually limited.
Fifth, TSV and stacking capacity utilization rate.
Sixth, Advanced Packaging capacity such as CoWoS.
Seventh, the per-wafer revenue difference between HBM and DDR5.
It will affect the capacity allocation of memory manufacturers.
Eighth, the duration, price adjustments, and minimum purchase commitments of long-term contracts.
Ninth, customer concentration.
An excessively high proportion of a single GPU platform will amplify the risk of qualification or product delays.
Tenth, operating cash flow and capital expenditures.
Technological leadership must ultimately be translated into cross-cycle free cash flow.
Conclusion: HBM Has Changed the Memory Industry, But Has Not Cancelled Investment Discipline
The industrial revolution of HBM is real.
It solves the most core bandwidth and energy efficiency bottlenecks in AI computing, elevating memory from standardized accessories to platform-level components that determine system performance. After HBM4 incorporates the advanced logic Base Die, the boundaries among memory manufacturers, wafer foundries, Advanced Packaging, and AI chip customers are further merging.
HBM has also reshaped the value distribution in the memory industry:
The core in the past was the cost per bit; in the future, competition will also involve bandwidth, power consumption, packaging, thermal management, customer customization, and system synergy.
However, HBM will not permanently free the memory industry from cycles.
When products are short and prices are high, capital will inevitably enter; when capacity, yield, and multi-supplier qualifications gradually mature, profits will be redistributed.
Therefore, the most accurate judgment on HBM is neither "just another conventional DRAM cycle" nor "an AI scarce asset that will always be in short supply."
But rather:
HBM is a growth track with real technical barriers and long-term demand, while also being a manufacturing track dominated by customer concentration, massive capital investment, and supply-demand cycles.
Long-term winners will not just be the companies that announce products earliest, but enterprises that can simultaneously achieve four things:
Pass customer qualifications on time for every generation, steadily improve mass production yields, control capital investments, and translate technological advantages into sustained free cash flow.
This is the true moat of the HBM industry in the AI era.