Core Summary
In Q4 2026, China's AI compute supply chain exhibited significant divergence in memory capacity structure. While contract prices for frontier-generation HBM3E/HBM4 stacks rose to over USD 200–300 per stack, procurement prices for mature-generation (HBM2/HBM2E class) stacks used in mainstream Chinese accelerator cards increased from an initial range of USD 30–40 to USD 95–120 per stack. Channel surveys indicate that driven by early-stage yield ramp-up costs (public reports cite approximately 25%, with targets to improve to 40%–50%) and domestic market-based bidding, spot quotes for domestically produced HBM circulating within China did not adopt a low-price strategy. Instead, they were priced approximately 5%–10% higher than comparable imported products from Samsung and SK hynix (channel estimate range; public reports suggest price differences between domestic and overseas markets are within20%), approaching the downstream customers' cost tolerance boundary of USD 110 per stack for mature generations.
This phenomenon is driven jointly by global supply structure shifts and expanding domestic demand. On one hand, the three major overseas memory manufacturers have locked more than 50% of their capacity into Long-Term Agreements (LTAs). With HBM4 entering mass production and shipment in 2026, they are fully shifting focus to R&D for HBM4E in 2027. This is expected to drive a year-over-year increase of 80%–121% in the global blended Average Selling Price (ASP) for HBM in 2027 (accounting for generational mix shift), while same-generation price increases are projected at approximately 40%–50%. On the other hand, under the pull of forecasted demand for 3.5 million–4 million high-performance AI chips nationwide in 2027, domestic compute vendors constrained by export controls are engaging in market-based bidding for limited domestic quotas.
To alleviate bandwidth memory supply bottlenecks and cost pressures, vendors both domestically and abroad are simultaneously advancing tiered memory architectures. Huawei, beyond the Ascend 950DT (equipped with high-bandwidth proprietary HiZQ 2.0/HBM2E, 144 GB/4.0 TB/s), introduced the Ascend 950PR for prefill and recommendation systems (equipped with low-cost proprietary HiBL1.0, 128 GB/1.6 TB/s, along with channel-sourced cost-optimized variants using domestic DDR/quasi-DDR). Channel surveys show the latter accounts for 35%–40% of total shipments in the 950 series. Internationally, NVIDIA recently evaluated scaling back its next-generation Rubin Ultra from an originally aggressive plan of 12-layer HBM4E to 8-layer HBM4. Cloud providers like Google are also exploring CXL + LPDDR memory pooling solutions combined with Marvell Structera X series controllers. On the manufacturing side, CXMT's total monthly capacity is expanding from 320,000–330,000 wafers/month to approximately 420,000 wafers/month by 2027. HBM3 entered equipment installation and trial production in Q3 2026, with a target shipment of approximately 50,000 wafer equivalents in 2027. Combined with YMTC's Phase 3 line moving toward full capacity of 300,000 wafers/month, the supply-demand gap for domestic high-bandwidth memory is expected to gradually ease in the second half of 2027.
I. Inverted Pricing Between Domestic and Overseas Markets: Why Does Mature-Generation Domestic HBM Carry a 5%–10% Premium Over Imports?
In the process of semiconductor localization in China, latecomers typically enter the market with price advantages. However, in the Q4 2026 AI compute supply chain, High Bandwidth Memory (HBM) exhibits a unique pricing structure.
1. Price Stratification Between Mature and Frontier Generations; Domestic Spot Premium Approx. 5%–10%
From a global pricing perspective, the current HBM market shows clear generational stratification: Contract prices for HBM3E (the primary purchase for North American cloud vendors) and newly mass-produced HBM4 in 2026 have reached highs of USD 200–300+ per stack. Meanwhile, mainstream Chinese accelerator cards still primarily rely on mature generations (HBM2/HBM2E class, approx. 16 GB per stack), with average procurement prices rising from an initial USD 30–40/stack to USD 95–120/stack (approx. USD 6–7 per GB). Driven by rising prices for storage and core supporting components, terminal quotes for accelerator cards from major domestic compute vendors such as Huawei Ascend and Cambricon generally increased by about 15% in the second half of 2026.
Taiwanese supply chain reports and domestic channel surveys both indicate that domestic HBM has not adopted a significant discount strategy, with quotes close to similar mature overseas products from Samsung etc. (public reports suggest price differences between domestic and overseas markets are within 20%). During the phase where domestic capacity from CXMT and others has not yet been released at scale, spot quotes for domestic HBM circulating within China are actually about 5%–10% higher than the import benchmark from Samsung and SK hynix (approx. USD 95–100/stack) (neutral estimate range 5%–7%).
2. Yield Costs, Export Controls, and Demand Forecast for 4 Million Chips
The temporary premium for mature-generation domestic HBM stems mainly from three factors: manufacturing costs, restricted cross-border channels, and expanded terminal demand:
▪ Early yield ramp-up drives up unit manufacturing costs: Public industry reports show that domestic HBM production lines are currently still in the yield ramp-up stage (current overall yield approx. 25%, with next-stage targets to improve to 40%–50%). Coupled with large depreciation of early specialized equipment and pilot production investments, upstream manufacturers need higher ex-factory prices to cover costs.
▪ Channel segmentation due to export controls: Since core buyers such as Huawei Ascend, Cambricon, and Hygon Information are on the Entity List, direct procurement of overseas manufacturer HBM2/HBM2E faces high compliance barriers. Incremental procurement demand concentrates back into limited domestic spot pools and local production lines.
▪ Demand pull for 3.5 million–4 million high-compute chips in 2027 (channel survey basis): As mainstream accelerator card VRAM capacity rises to 128 GB–196 GB+, VRAM consumption per card increases significantly. Based on supply chain scheduling and downstream procurement surveys, estimated demand for the Huawei Ascend series in 2027 is no less than 2.4 million units under conservative expectations, reaching 2.8 million–3.0 million units under neutral expectations (2026 shipment baseline approx. 1.2 million–1.6 million units). If combined with high-performance chips from Cambricon, Hygon Information, Alibaba Zhenwu PPU, Baidu Kunlunxin, etc., with single-card compute ≥ 1,000 TFLOPS (total forecast approx. 700,000–1 million units), total national demand for high-compute chips in 2027 is expected to reach 3.5 million–4 million units. Calculated roughly at an average of 150 GB VRAM per card, this pulls generalized high-bandwidth memory demand to 500,000–600,000 TB. Under market-based allocation mechanisms, major vendors are locking quotas through substantial advance payments (e.g., Hygon Information's Q3 report showed advance payments of CNY 5.885 billion; Alibaba Zhenwu PPU, Baidu Kunlunxin, etc., also densely locked orders in Q4).
Regarding price boundaries, customer feedback indicates an upper tolerance limit of approximately USD 110/stack for mature-generation HBM. Simultaneously, Samsung and SK hynix are evaluating dynamic adjustments to HBM2E quotes for the Chinese mature market. Influenced by overseas vendors' holiday schedules around Thanksgiving in late November and New Year's Day, October to late November 2026, and early January 2027 are critical negotiation windows for finalizing HBM supply quotas and prices for the entire following year.
II. Global Storage Capacity Mismatch: Why Does Tight Balance Persist Until 2028 Amidst HBM4 Mass Production and HBM4E Racing?
The supply shortage of domestic HBM is essentially a structural projection of the global DRAM industry's capacity transition towards HBM4/HBM4E generations.
1. Market Share of Three Major Manufacturers and Divergence in HBM4/HBM4E Mass Production
In Q3 2026, affected by slowed inventory buildup for smartphones and PCs, the quarter-over-quarter increase in global general-purpose DRAM narrowed to 15%–18%. However, server memory and HBM supply remained highly tight. Combining data from institutions like TrendForce and Counterpoint, the global three major memory manufacturers present a competitive landscape of "SK hynix leading, Samsung catching up, Micron constrained":
▪ SK hynix (Market share approx. 50%): Maintains dominant position in global HBM shipments. HBM4 entered mass production and shipment ahead of others in 2026; next-generation HBM4E is expected to enter mass production by the end of 2027. Due to large customer withdrawals, its available inventory remains at a low level of only 3–4 weeks.
▪ Samsung Electronics (Market share approx. 30%–35%): Aims to increase its share to 40% in the next product cycle. Samsung is most aggressive regarding HBM4E, planning to rush into mass production in Q2 2027, ahead of competitors.
▪ Micron Technology (Market share < 20%): Constrained by overall wafer capacity scale, the ramp-up pace of HBM4 is relatively gradual. Its HBM4E mass production timeline is expected to be after 2028.
2. 2027 Price Increase Forecasts: Same-Generation Rise 40%–50% vs. Blended ASP Rise 80%–121%
Since HBM uses dedicated packaging lines and consumes approximately 3 times the wafer area per unit capacity compared to standard DDR5, capacity allocated to HBM cannot easily flow back to general-purpose DRAM. Currently, more than 50% of the three major manufacturers' capacity has been pre-locked by key customers like NVIDIA and Qualcomm via Long-Term Agreements (LTAs), leaving only 30%–50% flexible capacity for spot price adjustments.
For global HBM price trends in 2027, two statistical bases must be distinguished:
▪ Same-generation product price increase (Channel survey basis): Under identical technology generations, driven by supply-demand gaps, HBM prices are expected to continue rising 40%–50% YoY in 2027 (still expected to rise 20%–30% in 2028);
▪ Full-market blended ASP increase (Institutional forecast basis): According to forecasts from institutions like TrendForce, due to the rapid increase in shipment share of high-premium HBM4 and HBM4E in 2027 (Product Mix Shift) combined with tight supply, the global HBM Blended ASP is expected to rise by 80%–121% YoY in 2027. The tight supply-demand balance for general-purpose DDR5 and LPDDR5 will also persist until late 2027 or early 2028.
3. Downstream Cost Constraints and NVIDIA Rubin Ultra Specification Rollback
High storage prices are forcing compute architectures both domestically and abroad to compromise on Return on Investment (ROI).
Multiple supply chain reports around October 2026 confirmed that NVIDIA, when planning its next flagship Rubin Ultra, has evaluated rolling back the originally aggressive 12-layer HBM4E configuration to an 8-layer HBM4 solution, correspondingly lowering the extreme bandwidth metrics per card. Under multiple constraints including significant price hikes by upstream memory manufacturers, limited early yields for 12-layer HBM4E, and downstream cloud vendors controlling Capital Expenditures (CapEx), even the overseas compute leader with the highest bargaining power has begun actively reducing the HBM stacking intensity per card.
III. System Architecture Tiering: From Ascend 950 (HiZQ 2.0 / HiBL 1.0) to Overseas CXL Memory Pooling Exploration
Facing restrictions on obtaining overseas HBM2E and high VRAM Bill of Materials (BOM) costs, Chinese compute vendors have fully shifted to tiered memory architectures during large-scale cluster deliveries in 2026–2027.
1. Ascend 950 Series: Tiered Coordination of High-Bandwidth HiZQ 2.0 and Low-Cost HiBL 1.0 / DDR
According to Huawei's official architecture release, SemiAnalysis teardown tests (October 2026), and supply chain channel scheduling surveys, total shipments of Ascend chips in 2026 are expected to be 1.2 million–1.6 million units (including approx. 1.0 million–1.2 million units of 910C, with new generation Ascend 950 series demand approx. 400,000 units). The Ascend 950 adopts a clear memory tiering strategy in product definition:
▪ High-Bandwidth Version Ascend 950DT (Accounts for approx. 60%–65% of 950 series shipments): Targeted at large model training and Decode stages. Official specifications include proprietary high-bandwidth storage HiZQ 2.0 (Capacity 144 GB, Bandwidth 4.0 TB/s; some batches also paired with overseas HBM2E). Constrained by high-bandwidth granule capacity and packaging bottlenecks, channel surveys indicate cumulative deliverable volume for950DT in Q4 2026 to Q1 2027 is approx. 70,000–100,000 units (e.g., DeepSeek's self-built data center demand exceeds 160,000 units, but initial allocation was only 40,000–50,000 units).
▪ Cost-Optimized Version Ascend 950PR and Domestic DDR Variants (Accounts for approx. 35%–40% of 950 series shipments): Targeted at Prefill, search/advertising recommendation algorithms (RecSys), and small-to-medium parameter inference. In official and SemiAnalysis test bases,950PR includes proprietary low-cost storage HiBL 1.0 (Capacity 128 GB, Bandwidth 1.6 TB/s; terminal whole-card price drops to approx. CNY 50,000 level); in supply chain channel surveys, some cost-reduced inference cards directly reconfigured with large-capacity domestic standard DDR/quasi-DDR solutions are also grouped into this cost-optimized category. Since recommendation systems and Prefill stages require large memory capacity but have low dependence on extreme multi-TB/s bandwidth, this tiered design bypasses high-order HBM supply bottlenecks while significantly reducing whole-machine delivery costs.
2. Ascend 960 Channel Forecasts and Overseas CXL + LPDDR Memory Pooling Exploration
Supply chain channel surveys indicate this memory tiering approach will continue into the next-generation Ascend 960 series in 2027 (channel estimates: sampling in Q12027, ramp-up in Q3, planned annual shipments approx. 400,000–500,000 cards, based on channel forecast). Regarding memory configuration, it is estimated that 80%–85% will be main versions equipped with next-generation high-order proprietary HBM (capacity doubled, bandwidth increased 2.5x), while retaining 15%–20% cost-optimized versions such as DDR5. Vendors like Cambricon and Hygon are also validating similar tiered configurations.
In overseas markets, utilizing CXL protocols and low-cost memory to relieve HBM pressure is also an important evolutionary direction. For example, Marvell has released the Structera X series CXL memory expansion controllers (sampling in 2026–2027) and is exploring cooperation with North American hyperscale cloud vendors including Google, aggregating low-cost LPDDR/DDR into TB-level shared memory pools via the CXL bus (industry rumors suggest Google is evaluating this for long-context inference expansion in large-scale TPU clusters in 2027), reducing dependence on single high-priced HBM at the system level.
IV. Domestic Capacity Expansion: CXMT Moving Towards 420k Wafers/Month and 50k HBM3 Wafer Targets; YMTC Phase 3 Progress
In core high-bandwidth scenarios such as trillion-parameter foundation model training/inference (e.g., new ultra-large models like DeepSeek-V4.1-Flash, Kimi k3.1 Pro (3 trillion parameters)) and high-concurrency multimodal video generation, HBM remains indispensable. Substantive alleviation of the high-bandwidth memory gap in China's compute base depends on the realization of capacity expansions by CXMT and YMTC.
1. CXMT: 2027 Total Monthly Capacity Moves Towards Approx. 420k Wafers, HBM3 Target Shipment Approx. 50k Wafers
Combining public reports from Counterpoint and TrendForce with production line surveys, the advancement pace of CXMT in total DRAM capacity and HBM3 mass production is as follows:
▪ DRAM Total Capacity Leap (320k–330k wafers/month → Approx. 420k wafers/month): In 2026, CXMT's Hefei Fab 2 (primarily invested in 4th-generation products) achieved full-load operation, with current total monthly capacity approx. 320,000–330,000 wafers/month. In 2027, with capacity release from the Shanghai new fab (channel estimates add 50,000–80,000 wafers/month; public reports from Counterpoint/TrendForce estimate 2027 total capacity expanding to approx. 420,000 wafers/month, net increase approx. 100,000 wafers/month), the overall wafer substrate will significantly expand.
▪ HBM3 Mass Production and Shipment Forecast: CXMT completed customer-side verification for HBM3 in 2025. In Q3 2026, supporting production equipment installation was completed, and small-scale mass production began. Channels estimate shipments of 20,000–30,000 wafers in H1 2027 (Q1-Q2), with a full-year 2027 cumulative shipment target of approx. 50,000 wafers (actual delivery scale remains constrained by subsequent yield ramp-up and packaging equipment arrival pace).
2. YMTC: Phase 3 Fully Localized Line Moves Towards 300k Wafers/Month in 2027
In the 3D NAND flash field supporting AI cache offloading (SSD Offloading), the production line built primarily with Chinese domestic equipment at YMTC's third wafer fab (Fab 3) has entered the stage of phased equipment entry and mass production ramp-up: driving total monthly capacity from approx. 200,000 wafers/month in Q3 2026 to approx. 230,000 wafers/month by end of 2026, and expected to reach 300,000 wafers/month after full load of Phase 3 in 2027 (consistent with public industry reports). Additionally, the combined capacity of the far-term planned Phase 4 and Phase 5 sites approaches the sum of the first three phases, expected to be gradually released after 2028.
3. Whole-Fab Localization Ratio and Customer On-Site Joint Verification
Regarding production line supply chain localization and client adoption:
▪ Equipment and Material Localization Rate: Counting the entire wafer fab, the equipment localization rate for CXMT's current expansion lines is approx. 30%, and material localization rate is approx. 50%. Among these, cleaning equipment and wet electronic chemicals have basically achieved domestic substitution (>80%), while high-end lithography machines and advanced photoresists still rely on overseas sources.
▪ On-Site Joint Tuning Shortens Adoption Cycle: Compared to the typical authentication cycles of >2 years for overseas Cloud Service Providers (CSPs), domestic cloud vendors (such as Alibaba) and server/AI compute enterprises adopt an engineer on-site joint tuning mode, completing signal testing and system adaptation directly within the wafer fab, significantly compressing the commercialization adoption time for HBM3.
Conclusion
Comprehensively considering public industry data and frontline supply chain surveys, the approx. 5%–10% price premium for mature-generation domestic HBM in Q4 2026 is the result of global manufacturer capacity concentrating on HBM4/4E (driving predicted 80%–121% surge in global HBM blended ASP for 2027), domestic lines being in early yield ramp-up stages, and rapidly growing demand for high-compute chips in China.
Facing memory constraints at this stage, China's compute industry chain is breaking through synergistically across three dimensions: Short-term relies on market mechanisms and dual domestic/overseas channels to lock core quotas; Medium-term utilizes tiered memory architectures of Ascend 950 (HiZQ 2.0 high-bandwidth version and 35%–40% HiBL 1.0/domestic DDR cost-optimized versions) to concentrate expensive HBM in core training and Decode inference; Long-term, as CXMT's monthly capacity moves towards 420,000 wafers in 2027, approx. 50,000 HBM3 wafers ramp up, and YMTC Phase 3 reaches 300,000 wafers/month full capacity, the domestic high-bandwidth memory gap will be gradually filled, pushing compute base costs and supply-demand back to equilibrium.
References and Data Sources:
1. Bryan Shan & Dylan Patel, *The Huawei-DeepSeek Symbiosis: Huawei Ascend 950PR Deep dive & µbenchmarks*, SemiAnalysis, October 21, 2026; Huawei Connect (HC) official architecture release materials for Ascend 950PR (HiBL 1.0) and 950DT (HiZQ 2.0).
2. TrendForce / Counterpoint Research, 2026–2027 Global HBM Market Share, HBM4/HBM4E Mass Production Evolution, Blended ASP Increase Forecasts, and CXMT/YMTC Capacity Tracking Reports (2026Q3–Q4).
3. Industry Chain Frontline Scheduling and Customer Procurement Survey Minutes (Covering 2027 Domestic High-Compute Chip Demand Estimates, Ascend 950/960 Shipment Structure Forecasts, CXMT HBM3 Wafer Scheduling, and Whole-Fab Equipment/Material Localization Rates, Sept–Oct 2026; Note: Non-public scheduling and proportion data marked as channel survey basis in text).
4. Q3 2026 Reports of Listed Companies Such as Hygon Information and Cambricon (Advance Payment and Inventory Disclosures) and Public Product Documentation for Marvell Structera X Series CXL Controllers.