Author: Peng Cheng
2D semiconductors, also known as atomic-layer semiconductors, are semiconductor materials whose core functional layers are only one or a few atoms thick. Represented by transition metal dichalcogenides (such as molybdenum disulfide), they are among the key materials in the post-Moore era. As the process nodes of silicon-based chips approach their physical limits, traditional silicon-channel semiconductor materials are nearing their performance ceilings. Leveraging their inherent advantage of atomic-level thickness, 2D semiconductors (such as MoS2, WSe2, and InSe) can achieve naturally strong gate control at short-channel scales with wafer-scale atomically flat structures, making them the most promising non-silicon new materials in the post-Moore era.
Currently, a global industrial consensus is rapidly forming. International wafer manufacturing giants such as TSMC (Taiwan Semiconductor Manufacturing Company), Intel, and Samsung, along with top research institutes like IMEC and IRDS, have clearly laid out their strategies in the 2D semiconductor track, predicting that it will be integrated as a core component into heterogeneous integration systems after the 1nm node. In June 2026, TSMC, in collaboration with ASML and imec, unveiled the first integration of 2D n/pFETs with a 50 nm contact gate pitch on 300 mm wafers at the VLSI Symposium, marking that international giants are accelerating the transition of 2D transistors from the laboratory to the production line. Under these circumstances, the domestic industry chain has also accelerated its full-chain layout, achieving breakthroughs from material preparation and independent equipment R&D to chip integration and ecosystem construction, and the 2D semiconductor industry chain is taking shape.
01. Material Breakthroughs and Equipment Localization: From "Able to Fabricate" to "Able to Mass Produce"
2D semiconductors are regarded as key materials for chip manufacturing in the post-silicon era, but the scalable, high-quality wafer preparation of 2D semiconductor materials is a prerequisite for their industrial application. Among them, Chemical Vapor Deposition (CVD) and Metal-Organic Chemical Vapor Deposition (MOCVD) are the key technologies for achieving scalable manufacturing of 2D semiconductor materials in the future.
In the field of equipment and material growth, the team led by Professor Wang Xinran from Nanjing University, in collaboration with its industrial transformation platform, Jimoxin Technology, has formed a deeply integrated closed loop of 'academic innovation—equipment development—process validation', achieving a series of breakthroughs in the preparation of wafer-scale 2D semiconductor single crystals. In October 2025, relying on the independently developed Oxy-MOCVD 200 ultra equipment by Jimoxin Technology (with 100% domestically produced core components), the team reported the world's first mass production preparation of6-inch 2D transition metal dichalcogenide semiconductor single crystals internationally through innovative substrate engineering technology. It is compatible with various materials such as MoS₂, WS₂, and WSe₂, and the unidirectional domain alignment rate of the 150 mm wafer exceeds 99%. In January 2026, the team collaborated with Wang Jinlan's team from Southeast University to develop a brand-new oxygen-assisted metal-organic chemical vapor deposition (oxy-MOCVD) technology, breaking through the bottleneck of growth kinetics regulation. This not only increased the average size of MoS2 crystal domains from the hundreds-of-nanometers scale to hundreds of micrometers, solving the mass production challenge of large-area uniform growth, but also fundamentally suppressed the carbon pollution problem. Based on this process, Jimoxin has completed deep customized upgrades of the equipment, providing downstream clients with plug-and-play process capabilities. Currently, the technical system covers mainstream 2D semiconductor materials such as MoS2, MoSe2, WS2, and WSe2. Building on this, Jimoxin has further taken the lead globally in achieving mass production of 8-inch 2D semiconductor single crystals. Its products have entered top research institutions such as the University of Cambridge and Fudan University, and it has reached cooperation with downstream chip manufacturing enterprises, bridging the critical gap from laboratory samples to production-line-level materials.
Besides mainstream n-type materials, the bottleneck in wafer-scale preparation of p-type 2D semiconductors has also been overcome. Similar to silicon-based electronic devices, wafer-scale n-type and p-type 2D semiconductor single crystals are the foundation and prerequisite for building 2D CMOS ICs (Integrated Circuits). To date, researchers have developed various n-type 2D semiconductor materials, among which MoS2 and WS2 have achieved wafer-scale single-crystal preparation; however, p-type 2D semiconductors with both high mobility and excellent stability remain extremely scarce, making wafer-scale single-crystal growth of such materials even more difficult. In July 2026, the team from the Institute of Metal Research, Chinese Academy of Sciences, achieved a breakthrough by successfully preparing large-area, high-performance p-type MoSi₂N₄ monolayer single-crystal wafers. This material system was pioneered by the team. Previously, only polycrystalline thin films could be prepared, where grain boundary gaps would significantly degrade device performance and were prone to damage during transfer processing. This research achieved directional growth and seamless stitching of the material through the step-guiding effect of a special single-crystal substrate, thoroughly making up for the long-standing core shortcoming of lacking high-quality p-type materials in 2D CMOS circuits.
In the direction of special materials, the research team led by Professor Peng Hailin at Peking University achieved the controllable preparation of ultra-thin, uniform ferroelectric thin films and their heterostructures at the wafer scale for the first time, and constructed high-speed ferroelectric transistors with ultra-low operating voltage (0.8V) and extremely high endurance (cyclable over 1.5×10^12 times). Its comprehensive performance significantly surpasses the existing industrial-grade hafnium-based ferroelectric systems, making it the ferroelectric transistor with the lowest known operating voltage, lowest energy consumption, and optimal endurance. It demonstrated a high-performance wafer-scale 2D ferroelectric material system internationally for the first time, providing a breakthrough material foundation and feasible technical path for developing high-energy-efficiency advanced chips.
02. Engineering Ecosystem Gradually Taking Shape, Bridging the Gap from Laboratory to Production Line
Breakthroughs in materials and devices ultimately need to be implemented in a standardized manufacturing system.
On July 9, 2026, the 8-inch 2D semiconductor engineering demonstration process line built by Yuanjiwei Technology was fully connected in Pudong, becoming a milestone for domestic 2D semiconductors transitioning from scientific research to industrialization. The process line was lit up in January 2026, and it took only over half a year to complete full-process equipment debugging and process optimization. Unlike small-scale laboratory trial platforms, it now possesses complete tape-out and engineering trial production capabilities, building a complete engineering chain from material preparation to chip integration. Prior to this, domestic 2D semiconductor research was mostly concentrated in university laboratories, with device preparation mainly relying on small-batch manual trials, which had a huge gap with industrial standards. After ten years of research, the Yuanjiwei team has bridged the complete process from wafer growth, integration processes, device modeling, circuit design to packaging and testing.
The supporting Process Design Kit (PDK) was simultaneously launched, further breaking down the connection barriers between design and manufacturing. The 500 nm PDK 0.1 version based on the 8-inch pilot line released by Yuanjiwei is the first process IP in the 2D semiconductor field compatible with mainstream EDA tool chains. It includes a full set of toolkits such as Pcell, DRC, LVS, and PEX. The process yield is greater than 99.99%, and various indicators have broken international records, basically approaching the level of silicon-based equivalent process nodes. In the future, it can support the design and wafer-scale manufacturing of 2D circuits at the 100,000-transistor level.
Along with the full connection of the production line and the release of the PDK, foundry services and the industrial ecosystem were launched simultaneously. University teams from Peking University, Tsinghua University, Shanghai Jiao Tong University, and Nanjing University have completed university-enterprise R&D signing with Yuanjiwei, and wafer foundry services are officially open to the scientific research end; enterprises such as Xi'an Xiandao Institute and Shanghai 2D Star Technology have also reached strategic cooperation in the industry chain, carrying out in-depth cooperation around process platform sharing, achievement transformation, and ecosystem co-construction. Local industrial support is also following up simultaneously. Chuansha Xinzhen in Shanghai, with the Yuanjiwei pilot line as the core carrier, is attracting the aggregation of upstream and downstream enterprises in the industry chain. At the municipal level, Shanghai has included 2D semiconductors as a key direction for future industry cultivation, making all-around efforts from scientific research, collaborative innovation to ecosystem cultivation, with the goal of forming a complete industrial closed loop of 'R&D—pilot production—mass production'. The proportion of existing silicon-based semiconductor equipment that can be reused in 2D semiconductor production lines is about 70%, which will not subvert the existing industrial system; rather, it will generate entirely new market increments in materials, equipment, manufacturing, and advanced packaging.
03. Application Landscape from Computing to Storage Continuously Expanding
Along with the maturation of the manufacturing system, 2D semiconductors are also expanding from logic computing to application scenarios such as storage.
In the field of logic computing, domestic researchers have completed the leap from devices to complex processors. In 2025, the world's first 32-bit RISC-V architecture microprocessor 'Wuji' based on 2D semiconductor materials was released. Adopting MoS2 material, it integrates 5,900 transistors with a thickness of only 0.7 nm. The yield of a single-stage inverter reaches 99.77%, achieving fully independent R&D across the entire chain from materials and architecture to tape-out, verifying the feasibility of building complex logic circuits with 2D materials. The processor can serially execute 37 types of 32-bit RISC-V instructions at a 1 kHz clock frequency, meeting the requirements of the RV32I integer instruction set. It features single-stage high gain and ultra-low off-state leakage current performance, making it suitable for IoT (Internet of Things) and edge computing scenarios.
In 2026, the teams of Wang Xinran and Qiu Hao from Nanjing University, in collaboration with the Suzhou National Laboratory and Huawei, further bridged the full process of 2D semiconductor chip design-process-manufacturing compatible with fab production lines, and successfully developed the world's first MoS2 multi-bit parallel microprocessor 'MAGIC-1000'. The transistor integration density set a new highest record for emerging non-silicon digital circuits, marking that China's 2D semiconductor research has entered a new stage of production line integration. Based on cross-hierarchical collaborative optimization, the team integrated 1,433 MoS2 transistors within an ultra-compact chip area under the 0.5 μm industrial process, successfully developing the 'MAGIC-1000' microprocessor. The chip adopts the RISC instruction set and consists of four main modules: instruction decoder, register file, arithmetic logic unit, and multiplexer. The integrated transistor density has increased by one order of magnitude compared to the previous international record, reaching 9,336/mm², comparable to mature silicon-based processes at the same node. The chip achieved multi-bit data parallel computing for 2D semiconductors for the first time, with a maximum operating frequency of up to 43 kHz, and integrated an on-chip register file on the 2D chip, eliminating the access latency and bandwidth bottlenecks caused by off-chip storage.
In the field of storage, the ultra-low leakage current characteristics of 2D semiconductors demonstrate unique strategic value. A joint team from Fudan University has developed the 2D semiconductor transistor with the lowest leakage current to date. The team achieved a record-low leakage current—equivalent to leaking only one electron every 9.15 seconds. The new DRAM memory chip built on this basis achieves an ultra-long data retention time of over 8,500 seconds at zero holding voltage, while balancing high-speed read/write and multi-capacity storage capabilities. The optimized capacitor-less dual-transistor DRAM (2T0C) achieves quasi-non-volatile memory operations, 5-bit storage precision, and nanosecond-level write speeds. Yuanjiwei has made DRAM a key layout direction. The ultra-low leakage current characteristics of 2D semiconductors can significantly reduce refresh power consumption, and are expected to be the first to land in edge-side and high-computing-power scenarios. In the future, combined with 3D stacking technology, DRAM capacity will be gradually increased. In July 2026, the Zhou Peng-Liu Chunsen team from Fudan University went a step further, clearly observing the non-volatile storage behavior of a single electron at room temperature for the first time, and successfully creating a device with the world's largest non-volatile quantum memory window—requiring the injection of only a single electron to achieve a memory window of 0.5 volts. This marks that charge information storage technology has reached the ultimate peak of 'one electron, one bit'.
Beyond computing and storage, 2D semiconductors possess irreplaceable advantages in more specialized scenarios. As an ultimate SOI material, 2D semiconductors have unique advantages in scenarios such as RF analog circuits, radiation-hardened communications, and brain-computer interfaces. In January this year, relying on the 'Fudan No. 1' satellite platform, the 2D semiconductor radiation-hardened RF communication system achieved space on-orbit verification for the first time. Meanwhile, 2D semiconductors can be fabricated into flexible and transparent devices, supporting device R&D in frontier fields such as optoelectronic sensing and quantum computing.
04. Conclusion
Currently, 2D semiconductors have completely stepped out of the laboratory and entered a brand-new stage of engineering verification and small-batch tape-out. From wafer-scale breakthroughs in material preparation to the engineering integration of manufacturing production lines, and then to the application implementation in multiple fields such as computing and storage, every link in the domestic 2D semiconductor industry chain is accelerating, initially forming a complete industry chain covering materials, equipment, manufacturing, design, and application.
In this emerging track of 2D semiconductors, international competition has fully unfolded. The formation of this emerging industry chain not only provides new possibilities for chip technology in the post-Moore era but also opens up a brand-new competitive dimension in the reshaping of the global semiconductor industry landscape.