[Relevant Companies Involved in This Article] JCET, TFME, Hua Tian Technology, Yongsi Electronics, Kaifa Technology (Payton Technology), SJ Semiconductor, ASE (Advanced Semiconductor Engineering), PTI (Powertech Technology Inc.), Amkor, Intel Foundry, Samsung, and SK hynix
I. Overview of Global Top Packaging Companies' Expansion in H1 2026
In the first half of 2026, global top packaging and testing companies intensively rolled out expansion plans, with the cumulative investment scale reaching a historic high. This is not a routine capacity supplement, but a comprehensive strategic positioning concerning the industry's discourse power over the next decade. Data from Yole Group shows that the global Advanced Packaging market size was approximately USD 53.1 billion in 2025, and is expected to reach USD 79.4 billion by 2030, with a CAGR of about 8.4%. Among them, AI, HPC, and data center applications have a CAGR of nearly 15%, becoming the most certain growth engine for the entire packaging and testing industry. [1]
Based on the latest industry dynamics, the top domestic and international companies that have clearly announced Advanced Packaging expansion plans or commenced construction in the first half of 2026 mainly include the following 12:
(Note: The investment amounts for Intel Foundry and Samsung are estimated values, calculated based on the assumption that packaging-related expenditures account for approximately 15% of their respective total capital expenditures for the full year 2026, for reference only.) [2] [3] [4]
▲ Announced Investment Scale of 12 Global Packaging Companies in H1 2026 and Global Advanced Packaging Market Size Forecast (2022-2030) (Source: Yole Group / Company Announcements)
II. Analysis of Core Advanced Packaging Technologies for Expansion: How Do the Top 12 Companies Place Their Bets?
In this capacity race, each company has carved out a differentiated expansion path based on its own technological endowments. The following is a detailed breakdown of the core packaging technology principles of the aforementioned companies.
(1) JCET: XDFOI™ Multi-Dimensional Ultra-High Density Fan-Out Packaging
JCET's Lingang project targets the AI and HPC markets. Its core weapon is the independently developed XDFOI™ full-series ultra-high density fan-out packaging solution. The biggest feature of this technology is that it does not require Through-Silicon Vias (TSV), but achieves ultra-narrow pitch interconnection between chips through high-density Redistribution Layers (RDL). Compared with traditional2.5D TSV solutions, XDFOI has significant advantages in cost control, warpage management, and long-term reliability, and focuses on the layout of CPO (Co-Packaged Optics) technology.
Source: JCET Announcement / XDFOI Technology White Paper
(2) TFME: VISionS™ 2.5D Chiplet Packaging
TFME is deeply bound to AMD, and its **VISionS™** platform adopts a typical 2.5D heterogeneous integration architecture: the main compute die and multiple HBM memory chips are densely bonded on a silicon interposer through microbumps; vertical conduction is achieved inside the silicon interposer through TSVs. This architecture achieves high-bandwidth interconnection of over 1TB/s between the compute core and memory.
Source: TFME Announcement / AMD Supply Chain Reports
(3) Hua Tian Technology: eSiFO™ and eSinC™ 3D Matrix Packaging
The second phase of Hua Tian Technology in Nanjing focuses on increasing investment in memory chip packaging and testing. Its **eSiFO™** silicon-based fan-out technology embeds chips by precisely etching grooves on a silicon substrate, featuring low stress and small warpage. eSinC™, on the other hand, focuses on 3D stacked memory packaging: it vertically stacks multiple layers of DRAM dies through TSV technology, primarily serving domestic memory customers.
Source: Hua Tian Technology Announcement / eSiFO/eSinC Technical Materials
(4) Yongsi Electronics: FH-BSAP™ Building-Block Advanced Packaging Platform
Yongsi Electronics' **FH-BSAP™** building-block platform allows Chiplets with different process nodes and functions to be flexibly combined like "building blocks". It achieves 2.5D heterogeneous integration through the Fan-out RDL layer and supports vertical stacking (3D), forming a highly flexible System-in-Package (SiP) solution.
Source: Yongsi Electronics Announcement / FH-BSAP Technical Materials
(5) Kaifa Technology (Payton Technology): High-End Memory Chip Packaging
Kaifa Technology focuses on the upgrade of high-end memory packaging and testing. Its technology roadmap covers FBGA/wBGA packaging for the mainstream market, as well as the combined technology of Flip Chip and TSV for high-end DDR5/HBM, primarily serving the high-end product lines of domestic memory customers.
Source: Kaifa Technology Announcement / Payton Technology Technical Materials
(6) SJ Semiconductor: SmartPoser™ 2.5D 3D Multi-Chip Integration
SJ Semiconductor is the only OSAT in mainland China that has mass-produced 2.5D silicon-based interposer packaging. Its SmartPoser™ technology is implemented on a 12-inch wafer-level platform and is currently the most mature mass production solution in China benchmarking against TSMC's CoWoS, having achieved batch delivery among domestic memory and AI customers.
Source: SJ Semiconductor Announcement / Dongsheng Hexin Groundbreaking Ceremony Press Release (2026-06-29)
(7) ASE (Advanced Semiconductor Engineering): FOPLP Fan-Out Panel Level Packaging
ASE places its bet on FOPLP (Fan-Out Panel Level Packaging), upgrading the packaging substrate from circular wafers to large-size rectangular panels. The single-run output efficiency is increased by 3 to 5 times, and the unit cost is significantly reduced by 30% to 50%, making it the ultimate weapon for cost reduction and efficiency improvement of large-size AI chips in the future.
Source: TrendForce / ASE Shareholders Meeting / Reuters Report on June 24, 2026
(8) PTI (Powertech Technology Inc.): FOPLP Leading the Mass Production of Panel-Level Packaging
PTI significantly increased its full-year 2026 capital expenditure from TWD 40 billion to over TWD 50 billion, of which approximately 75% is concentrated on FOPLP (Fan-Out Panel Level Packaging). As of Q1 2026, its FOPLP yield rate has reached an astonishing 94%—95%. PTI's Youda Plant has installed panel-level equipment capable of processing 5x reduced sizes, with the initial capacity of 3,000 panels per month in place in 2026, and full mass production expected to be achieved by mid-2027. Its technology has been adopted by international giants such as AMD and Broadcom, and continues to exert efforts in the field of CPO (Co-Packaged Optics). [8]
Source: PTI Earnings Call / Digitimes
(9) Amkor × TSMC: CoWoS US Localization Partnership
The CoWoS technology cooperated by Amkor and TSMC (Taiwan Semiconductor Manufacturing Company) is the absolute dominant player in current AI computing chips. It achieves ultra-high-density lateral interconnection between chips by densely flip-chipping AI chips and HBM on a silicon interposer through microbumps.
Source: TSMC/Amkor Joint Announcement on June 16, 2026
(10) Intel Foundry: EMIB and Foveros 3D Stacking
Intel's EMIB only embeds small "silicon bridges" inside the organic substrate, significantly reducing costs. Foveros is a 3D stacking masterpiece, achieving extremely high integration density through face-to-face microbumps or hybrid bonding.
Source: Intel Newsroom on June 18, 2026
(11) Samsung & SK hynix: HBM4E Packaging Showdown
SK hynix takes the lead in heat dissipation and bandwidth with its Advanced MR-MUF (Mass Reflow Molded Underfill) technology. Samsung, on the other hand, insists on the TC-NCF (Thermal Compression Non-Conductive Film) route, aiming to precisely control die thickness in higher-layer stacking.
Source: SK hynix Official Website on June 18, 2026 / Samsung Press Release on May 29, 2026
III. Will Advanced Packaging Capacity Remain Tight in the Next Five Years?
Faced with the aggressive expansion wave, will the release of capacity lead to severe overcapacity? In the next five years, Advanced Packaging capacity will exhibit the characteristics of "structural balance."
3.1 Supply and Demand Logic: Why the Rush for Expansion?
The core logic behind the expansion lies in the thirst for computing power and the slowdown of Moore's Law. The demand for memory bandwidth in AI chips is rising exponentially, and Advanced Packaging directly determines the final shipment volume of GPUs. Meanwhile, Chiplet heterogeneous integration has become a powerful tool to break the deadlock, evolving packaging technology from "protecting chips" to "creating systems." In addition, supply chain security drives the localized reconstruction of capacity. For domestic companies, "compensating for process limitations with packaging" is the core strategy for breaking through, and supporting the scaled mass production of domestic memory customers has become a rigid demand.
3.2 Capacity Assessment: From "Extreme Shortage" to "Structural Balance"
According to TrendForce's forecast, by the end of 2026, the extreme supply and demand imbalance will come to an end, and the gap is expected to narrow from 20% to about 10%. However, "narrowing" does not equal "overcapacity":
1.Rapid demand iteration: The demand for packaging area in the next-generation AI architecture doubles, and the capacity release speed can barely keep up with the demand slope.
2.High barriers for high-end capacity: Yield ramp-up for top-tier 2.5D/3D packaging takes 1 to 2 years, and truly high-quality capacity remains scarce.
3.Technological generational transition: The introduction of new technologies such as FOPLP and glass substrates will reshape the supply and demand curve, creating more incremental demand for edge AI and automotive electronics.
▲ Global Advanced Packaging Supply and Demand Analysis and Gap Forecast 2024-2030
3.3 Shift in Competition: From "Rushing for Capacity" to "Competing on Yield and Customer Binding"
In the next five years, the industry's focus will shift from mere investment scale to yield ramp-up and the depth of customer binding. Whoever can deeply bind with global top computing power/memory giants, and whoever can achieve the standard for HBM and Chiplet yields first, will truly transform capital expenditures into profits.
IV. Conclusion
This wave of Advanced Packaging expansion in the first half of 2026 is not just a simple replication of capacity, but a profound industrial upgrade.
In the next five years, the global Advanced Packaging market will maintain a CAGR of nearly 10%, marching towards a scale of USD 80 billion. In this process, whether it is TSMC deeply cultivating CoWoS, Samsung & SK hynix focusing on HBM4E packaging, ASE & PTI betting on FOPLP, or the Chinese forces such as JCET, TFME, Hua Tian Technology, SJ Semiconductor, Yongsi Electronics, and Kaifa Technology striving to catch up, all will write their own history in this "packaging race." The shortage of Advanced Packaging capacity may be alleviated to a certain extent in two to three years, but the battle for packaging technology innovation around higher density, lower power consumption, and better cost has just begun.
References
[1] Yole Group. (2026). Advanced Packaging Market & Technology Report 2026.
[2] TrendForce. (2026).ASE Targets FOPLP Mass Production by End-2026.
[3] Amkor Technology. (2026).TSMC and Amkor Technology Announce Long Term Partnership.
[4] Intel Corporation. (2026).Intel Appoints Seok-Hee Lee as EVP of Intel Foundry.
[5] JCET/TFME/Hua Tian Technology/Yongsi Electronics/Kaifa Technology/SJ Semiconductor.Company Announcements and Prospectuses.
[6] SK hynix/Samsung. (2026).HBM4E Product Roadmaps.
[7] SEMI. (2026).Semiconductor Equipment Forecast 2026.
[8] PTI (Powertech Technology Inc.). (2026).Q1 2026 Earnings Call Transcript.