Wafer Foundry
Recently, a series of significant events have occurred in the global wafer foundry sector, accelerating the commercialization process of advanced nodes at 2nm and below.
On July 13, TSMC (Taiwan Semiconductor Manufacturing Company) commenced mass production of its 2nm process simultaneously in Hsinchu and Kaohsiung; on July 23, AMD unveiled its sixth-generation EPYC server CPUs and Instinct MI455X AI accelerators built on the 2nm process at its annual Advancing AI conference; on July 25, Samsung Electronics signed a memorandum of understanding with Broadcom, announcing an expansion of their collaboration in memory, foundry, and advanced packaging over the next five years.
The AI (Artificial Intelligence) wave is driving a continuous surge in global computing power demand, making high-performance chips a core component of digital infrastructure. Against this backdrop, advanced nodes at 2nm and below represent more than just the iteration of technology nodes; they involve competition across multiple dimensions, including yield ramp-up, high-volume manufacturing, customer onboarding, and supply chain coordination.
01. Racing for Mass Production: Latest Updates and Technological Progress of the Top Four in Advanced Nodes
The current global advanced node landscape features a competitive and cooperative pattern among four major players: TSMC, Intel, Samsung, and Rapidus, with each focusing on different aspects of technology roadmaps and mass production schedules.
△Key Mass Production Node Roadmaps for the Top Four in Advanced Nodes (2nm/1.4nm)
#TSMC's 2nm node entered the mass production phase at the end of 2025, with capacity steadily expanding since 2026. According to public information, TSMC currently has five 2nm fabs simultaneously expanding capacity in Hsinchu, Kaohsiung, and other locations. In the second quarter of 2026, the 2nm process contributed approximately 3% of wafer revenue while maintaining an ultra-high yield rate. On July 13, the 2nm process officially commenced full-scale mass production in both Hsinchu and Kaohsiung.
From the perspective of customer structure, Apple has typically been the launch customer for TSMC's most advanced nodes over the past decade, continuing this pattern from the 20nm A8 to the 3nm A17 Pro. However, the customer landscape for the 2nm node has seen certain changes this time.
On July 23, AMD took the lead at its annual Advancing AI conference in unveiling the sixth-generation EPYC 9006 series server CPUs (codenamed Venice) and Instinct MI455X AI accelerators, both built on TSMC's 2nm process. AMD stated that the relevant solutions have entered the mass production phase and are expected to start shipping by the end of the third quarter. Specifically, EPYC Venice is based on the Zen 6 architecture and TSMC's 2nm process, featuring up to 256 CPU cores and 512 threads; the MI455X integrates approximately 320 billion transistors and 432GB of HBM4, utilizing a hybrid 2nm and 3nm process.
Although Apple did not secure the first launch at the 2nm node this time, supply chain information indicates that Apple has still locked in a substantial portion of the initial 2nm capacity to produce the A20 Pro chip, which will be featured in the iPhone 18 Pro series, expected to be released in September. Additionally, media reports suggest that Google will also become one of the customers for TSMC's 2nm mobile chips, with the Pixel 11 series, equipped with the Tensor G6 chip, scheduled for release on August 12.
Furthermore, TSMC's 1.4nm (A14) process is expected to enter risk production in the third quarter of 2027 and scale into high-volume manufacturing in 2028, offering a 10%–15% performance improvement at the same power or a 25%–30% power reduction at the same frequency compared to 2nm. Looking further ahead, the 1nm node and the A12 process featuring super power rails have also been planned for production in 2029. Technologically, TSMC's 2nm is its first process node to adopt gate-all-around (GAA) nanosheet transistor technology, while the company continues to advance the research and integration of backside power delivery and High-NA EUV (Extreme Ultraviolet) lithography.
#Intel, industry sources reveal that the yield rate of its 18A node is rapidly improving, and 18A has currently achieved mass production in select products. Intel's collaboration with Cadence is also advancing, with both parties integrating AI tools into the chip design flow to accelerate the development of 18A and 14A chips. The 14A node was originally planned for risk production in 2028 and high-volume manufacturing in 2029. However, the latest news indicates that Intel plans to initiate risk production on internal products in the second half of 2027 and fully launch high-volume manufacturing (HVM) in 2028, which is ahead of the previous schedule.
#Samsung, media reports indicate that the yield rate of its 2nm node has increased from the 20% range to the mid-50% range. It plans to commence trial production by the end of 2026 and enter high-volume manufacturing at its Taylor fab in the US in 2027. On July 25, Samsung Electronics announced the signing of a memorandum of understanding with Broadcom, with both parties planning to expand their collaboration over the next five years (until 2030), with an estimated cooperation scale exceeding $200 billion. According to the agreement, Samsung will utilize its 2nm and below advanced process technologies to provide foundry services for Broadcom's AI chips and high-speed communication chips; both parties will also develop Broadcom's next-generation AI accelerators based on Samsung's HBM technology, covering HBM4, HBM4E, and subsequent products; simultaneously, they will collaborate on the development of 2.3D/2.5D advanced packaging technologies.
Additionally, media reports suggest that Samsung's 1.4nm is expected to enter mass production in 2029, with the improved SF1.4+ version anticipated to be launched in 2030. Technologically, Samsung is based on the GAA architecture and leverages DTCO (Design Technology Co-Optimization) to optimize power and performance, while also laying out the R&D for the 1nm Forksheet architecture.
#Rapidus, as an emerging foundry backed by the Japanese government, plans to initiate high-volume manufacturing of 2nm in the second half of fiscal year 2027 (around October 2027), with an initial monthly capacity of 6,000 wafers, which is planned to expand to 25,000 wafers in 2028.
Currently, Rapidus has completed the prototype verification of 2nm GAA transistors and is collaborating with Canon to develop 2nm image processing chips, while also engaging with multiple overseas customers. Its 1.4nm node is planned to commence full-scale development within 2026, targeting mass production in 2029. Rapidus focuses on a "single-wafer processing" model to shorten delivery cycles, but the lack of initial yield ramp-up and large-scale commercial mass production experience remain challenges it needs to face.
02. Focal Points of the Advanced Node Game: The Triple Contest of Yield, Equipment, and Ecosystem
Entering the 2nm and below nodes, the process competition has extended from linewidth scaling to multi-dimensional system-level competition. Among these, yield and commercial realization capabilities, next-generation equipment and technology roadmaps, and advanced packaging ecosystems and customer lock-in have become the three most critical dimensions of current industry competition.
Yield rates directly impact foundry costs and customer profit margins. TSMC maintains a high level in 2nm yield, granting it significant initiative in pricing and capacity allocation; with the improvement in 18A yield, Intel's competitiveness in the external foundry market has been enhanced; Samsung and Rapidus, however, still need to further verify their yield stability in subsequent mass production processes.
In terms of equipment and technology roadmaps, the GAA architecture has become the mainstream technology choice for the 2nm node—TSMC's 2nm is its first node to adopt GAA technology, Intel has taken the lead in integrating High-NA EUV into mass production, and technologies such as backside power delivery and DTCO have also become key variables for energy efficiency optimization.
In terms of the advanced packaging ecosystem, the demand for heterogeneous integration in AI chips continues to rise, and packaging technologies (such as EMIB-T, CoWoS, and 2.3D/2.5D integration) are increasingly carrying more weight in the competition for customer orders.
From the current competitive landscape, TSMC holds a dominant position in the global wafer foundry market. According to data from TrendForce, the combined revenue of the world's top ten wafer foundries in the first quarter of 2026 reached $47.95 billion, a quarter-on-quarter growth of 3.7%, setting a new single-quarter record. Benefiting from the continuously strong shipment demand for AI server GPUs/xPUs, TSMC's revenue increased by 6.3% quarter-on-quarter to $35.86 billion, with its market share further climbing from 70.4% in the previous quarter to 72.3%; although Samsung Foundry (excluding system semiconductors) received some advance stocking orders from the TV and PC/NB supply chains, the momentum was roughly offset by the off-season effect for smartphones, resulting in a 5.8% quarter-on-quarter revenue decrease to $3.2 billion, with its market share dropping to 6.5%, maintaining its second-place ranking.
Beyond TSMC, various manufacturers have chosen differentiated competitive paths based on their own technological endowments and resource conditions. Relying on the first-mover introduction of the 18A process and High-NA EUV, Intel strives to establish a presence in the external foundry market; leveraging its "foundry + memory" vertical integration capabilities, Samsung is exploring the direction of an integrated AI chip manufacturing platform; Rapidus, on the other hand, enters the market with its "single-wafer processing" model and differentiated pricing, gaining support from the Japanese government and industry.
03. Future Trends of Advanced Nodes: Node Windows, AI Empowerment, and Foundry Model Transformation
Looking ahead, the industry believes that the competition for advanced nodes at 2nm and below is expected to evolve along three main directions.
The decisive window for nodes is concentrated between 2027 and 2029. The commercialization process of 2nm has already accelerated in the second half of 2026, while the competition for the 1.4nm node is expected to unfold intensively between 2028 and 2029: TSMC's A14 is expected to enter high-volume manufacturing in 2028, Intel's 14A is planned for mass production in 2029, Samsung's SF1.4 has been adjusted to 2029, and Rapidus has also set its 1.4nm mass production target for 2029.
The penetration of AI tools throughout the entire foundry process is deepening, and "design-manufacturing collaboration" is gradually becoming an industry trend. Foundry services are no longer limited to the manufacturing stage; AI technology is being introduced into design and process optimization flows. Intel and Cadence have already collaborated on AI-assisted chip design; Samsung participates in collaborative development with customers from the early design stage, covering architecture optimization, process tuning, and packaging integration. As a collaborative optimization method connecting design and process, DTCO is considered one of the important pathways to improve performance when process scaling approaches its limits.
The form of competition is shifting from "pure wafer manufacturing" to "system-level foundry". As the cost and difficulty of process scaling continue to rise, the weight of advanced packaging in improving overall chip performance is constantly increasing. TSMC continues to invest in packaging technologies such as CoWoS; Intel's EMIB-T packaging yield is reported to be 98%; Samsung, through its collaboration with Broadcom, is advancing simultaneously across multiple stages of "memory + foundry + packaging," exploring the implementation path for integrated solutions.
Against this backdrop, the competition among manufacturers is evolving into a comprehensive capability comparison of "advanced manufacturing + advanced packaging + EDA ecosystem". The resource endowments of different manufacturers determine their respective path choices: TSMC focuses on the pure foundry model and extends to packaging and other stages; Samsung, relying on its dual layout in memory and foundry, presents a differentiated competitive window in supply chain integration.
The competition for advanced nodes at 2nm and below is one of the most capital-intensive and technologically complex fields in the current semiconductor industry. Against the backdrop of steadily growing AI computing power demand, the competitive and cooperative landscape of the four companies and its evolution not only concerns the rise and fall of their respective market positions but will also profoundly impact the technological direction and supply chain landscape of global digital infrastructure. The final outline of this competition remains to be revealed by time.
#Wafer Foundry #Advanced Nodes #Semiconductor #AI