[Relevant Companies Involved in This Article] Intel, NVIDIA, TSMC, Samsung Electronics, Samsung Electro-Mechanics, SKC, Absolics, AGC, Corning, NEG, SCHOTT, OHARA, LPKF, Onto Innovation, SCHMID Group, EV Group, Applied Materials, BESI, ASMPT, SUSS MicroTec, EBARA, MKS Instruments, DuPont, Ajinomoto, Sekisui Chemical, DNP, FICT, PLANOPTIK, Tecnisco, ASE, Amkor, Broadcom, Kaisheng Technology, Caihong Shares, GeBiJia, Kibing Group, Dongxu Optoelectronic, Woge Optoelectronic, Tongge Micro, Boshin Cheng, Fozhi Xin, Sandieji, Yuntian Semiconductor, AKM Meadville, DEER Laser, Han's Semiconductor, HGLASER, Delphi Laser, Yingnuo Laser, Guihua Intelligent, ACM Research, Xin Chengnuo, NAURA, Piotech, Dongwei Technology, Huicheng Vacuum, HWATSING, Kingsemi, Stepping, Weijian Intelligent, Tancheng Technology, Sanfu New Material, ATEN, Huahai Chengke, Longhua Technology, Changchuan Technology, AccoTEST, JCET, TFME, Hua Tian Technology, Shenghe Jingwei, Yuntian Semiconductor, Fozhi Xin, Sandieji (Guangdong), Zhongji Innolight, Accelink, HGGenuine, etc.
I. The Hotspot Is Not "Glass Substitution", but Packaging Architecture Reshaping
Today, GPUs, ASICs, HBMs, I/O chiplets, and optical engines need to collaborate within the same system. Packaging area, interconnect count, power delivery density, warpage, and thermo-mechanical stress are all rising simultaneously. Material selection has thus escalated from a backend engineering issue to an architectural issue.
Vera Rubin is a microcosm of this demand-side shift. According to official NVIDIA data, the Rubin GPU integrates 336 billion transistors, features up to 288 GB of 12-Hi HBM4, and achieves a peak memory bandwidth of 22 TB/s; on the networking side, Spectrum-X Ethernet Photonics pushes CPO into a clear product roadmap. These figures prove that larger packaging, more memory stacking, higher I/O counts, and shorter electrical interconnect distances have become system constraints. However, it must be emphasized: NVIDIA's public materials have not confirmed that the Rubin GPU packaging adopts glass core substrates, glass interposers, or TGV. Rubin's significance to glass is that the demand logic is amplified, not that the terminal BOM has been confirmed.
Hybrid bonding solves ultra-fine pitch connections between chiplets, TSV handles vertical interconnects within silicon stacking, TGV handles panel-level vertical interconnects for glass cores or glass interposers, and RDL completes planar fan-out. They operate at different levels and can be stacked within the same heterogeneous package.
Therefore, current advanced packaging can be summarized into five converging hotspot mainlines.
These five mainlines collectively explain the source of the glass hype: glass is more likely to first enter high-value scenarios extremely sensitive to packaging size, frequency, warpage, or optoelectronic integration, rather than comprehensively replacing organic substrates in the short term. Joint technical materials from Onto Innovation and LPKF also explicitly point out that organic substrates will continue to evolve and exist for a long time.
II. Material Foundation: Why Glass Enters Advanced Packaging at This Time
2.1 First, Break Down "Glass Substrate" into Four Different Products
Industry discussions often confuse carrier glass, glass core, glass interposer, and glass optical platform. Yole's public classification explicitly distinguishes them into glass carriers, glass core substrates, glass interposers, TGV, and other emerging glass technologies.
2.2 Glass Advantages Stem from "Designable Material Combinations," Not a Single Parameter
Glass is not a fixed material. Borosilicate, alkali-free, aluminosilicate, fused silica, and photosensitive glass differ significantly in CTE, dielectric constant, dielectric loss, strength, machinability, and cost. The TGV process must co-design the glass grade with via formation, metallization, thermal budget, and end applications.
The first value is dimensional stability and low warpage potential. Large-size organic substrates are affected by moisture absorption, thermal expansion, and interlayer material differences, increasing pressure on pattern alignment and packaging warpage. Intel's official roadmap states that, compared to organic substrates, glass can achieve approximately 50% lower pattern distortion and potentially support up to 10x interconnect density; these are corporate self-tests and design potentials, and should not be written as universal mass production cross-evaluations.
The second value is electrical performance and high-frequency compatibility. Glass itself is insulating, has low moisture absorption, and a flat surface, and can achieve lower dielectric loss through formulation. For RF, millimeter-wave, CPO, and high-speed SerDes, material loss, geometric stability, and planar routing precision can collectively reduce signal integrity pressure. Its transparency also provides freedom for laser debonding, optical inspection, and potential waveguide/passive device integration.
The third value is large-area manufacturing potential. AGC's public TGV product specifications cover 150/200/300 mm wafers and 510×515 mm panel examples, with glass thicknesses of 0.1—1.0 mm and via diameters of 20—150 μm, offering straight, tapered, or hourglass vias. LPKF targets 600×600 mm class panel manufacturing as a glass core application direction. Special attention is needed: these are product or platform statements from different suppliers and cannot be directly equated to the stable capability of the same customer's mass production line.
2.3 Glass Is Not "Better Silicon," Nor Is It "Harder ABF"
Figure: Hierarchical relationship of glass, TGV, TSV, hybrid bonding, and CPO
The main constraints of glass also come from the material itself. Its thermal conductivity is far lower than that of silicon and copper, and it cannot automatically solve the heat dissipation of AI chips; its brittleness means that edge cracks, scratches, and bulk defects may be amplified during laser processing, wet etching, CMP, mounting, or thermal cycling; the CTE mismatch between Cu and glass will also form interface stress, copper bumping, cracking, and delamination risks. Therefore, the material advantages of glass can only be realized through structural design, low-temperature processes, copper volume control, stress buffer layers, thermal paths, and full-process inspection.
III. Full TGV Process: From "Drilling Vias" to Panel-Level Yield Closed-Loop
TGV (Through-Glass Via) refers to the vertical conductive channels formed in glass cores or glass interposers. Compared to TSV, the inner wall of glass is inherently insulating, usually not requiring the prior deposition of an independent via wall insulation layer; but this does not mean the process is simple. The glass-metal interface still requires surface activation, adhesion/barrier layers, and continuous seed layers. Deep via coverage and thermal cycling reliability remain core barriers.
Figure: TGV glass core cross-section, copper interconnects, and RDL
3.1 Eight-Step Process Chain and Defect Superposition
Figure: Full TGV process chain and defect superposition
The first step is glass formulation and raw sheets. Semiconductor-grade glass raw sheets must control not only thickness, TTV, Ra, and CTE, but also bubbles, inclusions, stones, microcrystals, scratches, edge cracks, and bulk stress. Femtosecond lasers can improve processing precision but cannot "repair" raw sheet defects; conversely, laser-induced stress and subsequent wet processes may transform invisible defects into breakage or crack sources.
The second step is via formation. Selectable routes include direct laser drilling, selective laser etching, LIDE, wet/dry etching, and photosensitive glass. The mainstream "laser modification + wet etching" path first uses ultrafast lasers to alter the local glass structure, then forms through-vias via selective etching. Evaluating equipment cannot just look at via speed; it must simultaneously consider via position accuracy, top/waist/bottom diameters, taper angle, sidewall roughness, chipping, and microcracks.
The third step is wet via enlargement and cleaning. The selection ratio, temperature, concentration, time, flow field, and residue control of HF or buffered systems jointly determine the via shape. Side etching will change the waist diameter and taper angle, while insufficient cleaning will contaminate subsequent seed layers; breakage, EHS, and waste liquid recovery make wet equipment a significant cost and safety constraint in mass production lines.
The fourth step is surface activation, adhesion/barrier, and seed layer. PVD, electroless plating, ALD/CVD, or hybrid methods may be used to establish a continuous conductive starting layer. Hourglass vias, re-entrant vias, or high aspect ratio vias will generate shadow zones, leading to local seed loss; double-sided flip PVD, conformal deposition, or electroless plating reinforcement may be necessary. Seed layer discontinuity will be amplified into voids, seams, and local high resistance in the next step.
The fifth step is copper electroplating or hybrid filling. Full copper filling has low resistance, but large copper volume and high thermo-mechanical stress; sidewall copper plating + dielectric via filling, via filling and re-drilling, conductive paste, or hybrid structures can trade off between electrical performance, stress, manufacturability, yield, and cost. Additive systems, current waveforms, via shape, mass transfer, and panel flow fields must be co-designed; "copper fully filled" is not the only correct answer.
The sixth step is planarization and RDL. Overplated copper needs to be removed via CMP or etch-back, and fine-line RDL, dielectric layers, and pads are formed on both sides of the glass. Copper dishing, erosion, over-polishing, residues, and large panel distortion will cause RDL open/short circuits and alignment loss. SCHMID's released full-panel process platform integrates wet, PVD, ECD, and CMP into a single embedded circuit flow, indicating that glass industrialization will drive full-panel planarization and circuit equipment, not just laser via drilling equipment.
The seventh step is bonding, mounting, and packaging integration. Glass platforms must also collaborate with chiplets, HBM, optical engines, temporary carriers, underfill, TIM, and solder/copper pillars. Particles, warpage, overlay, Known Good Die (KGD), and rework strategies will determine whether high-value chiplets can safely enter packaging.
The eighth step is inspection, reliability, and data closed-loop. AOI handles missing vias, positions, and top/waist/bottom diameters; X-ray/CT and SAM detect via internal voids, delamination, and hidden cracks; interferometry monitors CMP dishing/protrusion; link resistance and ATE connect to panel-level electrical properties; after HAST, HTS, and thermal cycling trigger potential failures, root causes are traced back through EMMI/OBIRCH, FIB/SEM/TEM, and material analysis. Only by correlating parameters from each station to the final panel-level results do the "capabilities" of equipment and materials become reproducible manufacturing windows.
3.2 Under Millions of Vias, "99.9% Single-Via Yield" Is Almost Meaningless
Figure: Theoretical panel-level yield cliff under millions of vias
Assuming each critical via is independent and the failure of any critical via leads to the failure of the entire panel, then:
Panel-level full yield = (1 − critical via defect ppm / 1,000,000) ^ number of critical vias.
When a panel has 1 million critical vias, a single-via yield of 99.9% means a defect rate of 1,000 ppm per via, and the theoretical panel-level full yield approaches zero. Even if the defect density is reduced to 1 ppm, the theoretical panel-level yield is only about 36.79%; only when reduced to 0.1 ppm is it about 90.48%. Real-world designs can modify this simple assumption through redundancy, non-critical via partitioning, screening, rework, and defect clustering models, but its engineering implication remains unchanged: mass production cannot just report "single-via yield"; it must simultaneously report defects per million vias, panel-level electrical yield, defect distribution, and screening strategies.
This also explains why the core equipment chain for TGV must include inspection and software. Onto/LPKF points out that early microcracks can expand into fatal defects in subsequent processes, and via position and shape will affect double-sided electrical connections and plating integrity; incoming glass, via formation, copper plating, and CMP must be measured station by station. [3] Therefore, high-speed AOI capable of scanning millions of vias in minutes, in-via X-ray/acoustic inspection, cross-station data traceability, and defect classification may have a value no less than via formation itself.
IV. Material Industry Chain: The Invisible Formulas That Truly Determine Mass Production
The difficulty in the material industry chain lies in the fact that a large amount of value is not reflected in the visible structure of the final product, but is hidden in glass formulations, cleaning, surface activation, targets, additives, photoresists, dielectrics, and CMP slurries. Batch fluctuations in any material can be amplified through via formation, metallization, and thermal cycling.
4.1 Electronic-Grade Glass Raw Sheets: Defect Budget Starts from the Furnace
Glass raw sheet suppliers need to control five categories of indicators simultaneously. The first category is bulk defects, including bubbles, inclusions, stones, striae, and microcrystals; the second is surface and edge quality, including scratches, chipping, Ra, and subsurface damage; the third is geometry, including thickness, TTV, flatness, and large panel warpage; the fourth is material physical properties, including CTE, Dk/Df, moisture absorption, strength, softening point, and chemical resistance; the fifth is batch-to-batch consistency and traceability. Scale manufacturing experience in display glass or cover glass is an important foundation but cannot be automatically equated to semiconductor-grade TGV raw sheet capability.
From a formulation perspective, alkali-free glass is suitable for electrical insulation and packaging substrates; borosilicate glass balances thermal expansion and processing; aluminosilicate glass has higher strength; fused silica has low loss and low CTE, but processing and costs are higher; photosensitive glass provides specific via formation routes. Selection cannot be separated from target via diameter, panel size, metallization, and thermal budget.
4.2 Wet, Seed Layer, and Electroplating Materials Determine "Whether Vias Can Become Interconnects"
Wet materials include HF/buffered etch systems, cleaners, activators, and filtration/recovery systems. The key is not the chemical names, but the selection ratio, concentration and temperature stability, metal ion contamination, residues, particles, and EHS. Seed/barrier materials may involve Ti, TiW, Cr, Cu targets, catalysts, and electroless plating systems; their task is to achieve continuous coverage on high aspect ratio via walls and maintain Cu/glass adhesion during thermal cycling.
Electroplating materials consist of high-purity copper salts, suppressors, accelerators, levelers, complexing agents, and online analysis systems. Additive formulations need to coordinate with via shape, mass transfer, and power waveforms to reduce voids and pinch-off while controlling overplating and internal stress. For glass substrates, solution stability, in-plane concentration, and filtration circulation will directly affect the consistency of millions of vias' distribution.
4.3 RDL, CMP, and Packaging Materials Connect Local Interconnects to System Reliability
RDL requires photoresist/dry film, PI/PBO/BCB dielectrics, copper, and surface treatment materials; CMP requires slurry, polishing pads, cleaning, and endpoint control; packaging integration also requires temporary bonding adhesives, debonding layers, underfill, TIM, solder, and copper pillars. The low thermal conductivity of glass means TIM and heat dissipation structures are more critical, while glass brittleness requires bonding/debonding and underfill to operate under low-temperature, low-stress conditions.
The validation cycle for material companies is often longer than single-equipment demonstrations because once a material changes, it simultaneously affects via shape, interfaces, stress, dielectric properties, and lifespan. The true barrier to entry is not "whether a bottle of formula can be provided," but whether a stable batch window, failure database, and change management can be delivered under the customer's specified glass grade, via shape, equipment, and reliability conditions.
V. Equipment Industry Chain: From Single-Equipment Parameter Competition to Full-Line Synergy
Figure : TGV material, laser, wet, metallization, and inspection equipment chain
Figure : Value chain of material—equipment—process control—substrate and system
5.1 Laser Equipment: Via Speed Is Just the Starting Point
Ultrafast laser equipment consists of a laser source, beam shaping, scanning galvanometers, precision motion platforms, auto-focus, temperature control, visual positioning, and software. Mass production evaluation includes at least the number of modified vias per unit time, position accuracy, via diameter distribution, chipping/cracks, thermal impact, compatibility with different glass grades, full-panel consistency, equipment utilization rate, and maintenance costs. Only publishing the best via diameter or single-sheet speed cannot prove the equipment's manufacturability during long-term operation on large panels.
The core advantage of selective laser etching/LIDE is modifying first and then wet etching to form vias, which can achieve higher aspect ratios and lower thermal damage; but it expands equipment competition from "single laser equipment" to a combined window of "laser—wet—inspection." LPKF's technical materials also list low sidewall defects, no microcracks, and large panel uniformity as mass production requirements for glass core substrates.
5.2 Wet, PVD/ALD/CVD, and Electroplating: Panel Uniformity Determines Whether Capacity Is Real
Wet equipment must control flow field, temperature, concentration, selection ratio, breakage, and drying water marks on large-area glass. PVD faces via wall shadows and double-sided processing; ALD/CVD provides better conformality but needs to balance speed and cost; electroless plating can reinforce continuous coverage but increases formula and waste liquid management. Electroplating equipment must uniformly handle in-via mass transfer, in-plane current distribution, additive monitoring, and copper stress.
For panel-level equipment, nominal panel size does not equal effective capacity. What truly affects cost is usable area, edge exclusion, breakage rate, changeover time, double-sided processing methods, solution lifespan, maintenance cycles, and good area throughput. If equipment manufacturers can only obtain ideal cross-sections on display samples and cannot correlate process capability indices, defect ppm, and panel-level electrical properties, they are still in the early stages of engineering.
5.3 CMP, RDL, Bonding, and Inspection Upgrade "Back-End" to Front-End Level Control
CMP needs to simultaneously control copper dishing, dielectric erosion, full-width flatness, and breakage on low-rigidity, fragile large panels; RDL lithography must compensate for glass panel distortion, achieve double-sided alignment, and control fine-line open/short circuits; temporary bonding/debonding and flip-chip mounting must protect high-value chiplets. Hybrid bonding further pushes particle, surface roughness, overlay, and cleaning standards to the front-end level.
Inspection equipment is the most easily underestimated yet most likely to generate compound interest link. AOI needs to find missing vias, positions, and shape anomalies among millions of vias; X-ray/CT, SAM, and interferometry must identify in-via voids, delamination, and CMP topography; electrical testing and reliability must connect to equipment logs. The iST case shows that by using X-ray for positioning, cross-sectioning, and SEM to identify uneven copper filling and voids, and then adjusting plating parameters and time, filling integrity can be improved.
Equipment value is ultimately determined by a multiplicative formula: Good area throughput = Nominal capacity × Utilization rate × Process yield × Panel-level electrical yield. If any item approaches zero, no matter how beautiful the other parameters are, they cannot be translated into commercial output. The opportunity for domestic equipment is therefore not just to substitute imported single machines, but to solidify process windows, consumables, maintenance, and data models into full-line capabilities through joint development with material, chemical, substrate, and OSAT companies.
VI. Application Frontier: How HBM, Chiplet, and CPO Connect to Glass Platforms
6.1 HBM and Chiplet: Glass Is Located at a "Lower" System Platform
Inside HBM stacking, TSV or hybrid bonding is still relied upon; logic chiplets can use SoIC/hybrid bonding; interposers bear fine-line lateral interconnects; while glass core/TGV can provide mechanical support, double-sided RDL, power delivery, and system connections at a lower level. Therefore, "TGV replaces TSV" is a false proposition; a more reasonable architecture is layering different vertical interconnects by scale.
When packaging size expands, the warpage and pattern alignment pressure of organic carriers increases, making glass's dimensional stability and tunable CTE more valuable; but the thermal flux of HBM and GPU also makes glass's low thermal conductivity a constraint. Glass platforms must be co-designed with thermal diffusion layers, TIM, copper structures, and system cooling, and cannot be explained solely by dielectric advantages.
6.2 CPO: The Most Imaginative yet Most Cautiously Verified Scenario for Glass
Figure: Electrical and optical interconnect synergy on glass platforms
The goal of CPO is to bring optical engines closer to switching ASICs or computing chips, shortening high-speed electrical links, thereby reducing network power consumption and signal loss. NVIDIA has publicly adopted CPO in Spectrum-X Ethernet Photonics and provided energy efficiency and availability improvement metrics compared to traditional pluggable networks. This confirms the productization trend of CPO but does not automatically confirm that a specific glass substrate supplier has entered its BOM.
Glass's attractiveness to CPO comes from four points. First, low loss and dimensional stability benefit high-speed electrical interconnects; second, transparency and refractive index designability provide space for waveguides, coupling structures, and passive optics; third, TGV can provide vertical power and signals around electrical and optical modules; fourth, panel-level manufacturing may improve the area utilization of optoelectronic modules. Corresponding validation must also cross electrical and optical domains: insertion loss, return loss, coupling tolerance, thermal drift, packaging stress, laser lifespan, testability, maintainability, and supply chain standards are all indispensable.
6.3 EDA/PDK Is the "Invisible Equipment"
When glass formulation, TGV geometry, RDL, copper stress, optical waveguides, and packaging thermal paths are coupled, design and manufacturing can no longer be handed over serially. The industry needs material models for glass, TGV parametric cells, signal/power integrity models, thermo-mechanical models, optoelectronic co-simulation, DFM rules, test structures, and yield learning databases. Without PDK and standardized design rules, customers have to redo material and reliability development every time they onboard, and commercialization speed will be repeatedly pulled back to the engineering sample stage.
VII. Industry Landscape: The Real Position of Global Pioneers and the Domestic Chain
7.1 Global: Roadmaps, Low-Volume Manufacturing, and Equipment Ecosystems Are Formed, but HVM Is Still Converging
Intel is a representative of the chip and packaging platform route. Its official materials state that it has conducted over ten years of glass substrate research and reliability evaluation, planning to provide complete solutions in the latter half of this decade, initially targeting large packaging and high-speed scenarios such as data centers, AI, and graphics. This shows that demand and long-term R&D investment are clear, but "the latter half of this decade" cannot be compressed into a specific mass production year.
Absolics is a representative of glass core manufacturing engineering. Its website states that SVM facility construction and commissioning were completed in 2024, and commercialization will be promoted in 2026; the US NIST precisely defines the Covington facility as a "low-volume manufacturing facility," and the project is used for material, tool, design, and prototype integration validation. [9] Therefore, its reasonable stage is low-volume manufacturing/customer validation infrastructure is formed, while HVM customers, yield, and volume have not been disclosed.
AGC provides relatively clear TGV product specifications, LPKF provides LIDE via formation processes and equipment, Onto Innovation emphasizes the measurement closed-loop from incoming materials to CMP, and SCHMID connects wet, PVD, ECD, and CMP to a full-panel platform; these participants show that the global ecosystem has shifted from "material feasibility" to "process integration and process control."
7.2 Domestic: Coverage Has Increased, but Needs to Move from "Lists" to "Evidence Grading"
Domestic companies have covered special glass raw sheets, ultrafast lasers, wet processes, PVD/CVD, electroplating, CMP, direct-write lithography, bonding, inspection, glass core processing, packaging and testing, and optical modules. This coverage has strategic significance because glass substrates are not a single-equipment track; local synergy can significantly shorten the iteration cycle for formulations, via shapes, copper plating, and inspection.
However, display glass, cover glass, or special glass experience of material companies can only prove capability proximity; advanced packaging delivery, sample testing, or first-equipment shipment of equipment companies can only prove engineering entry; samples, patents, production line planning, or customer sampling of substrate companies can only prove validation progress. Only when customer certification, repeat orders, stable utilization, full-panel yield, reliability lifespan, and revenue disclosure appear simultaneously can the stage be elevated to commercial mass production.
This matrix is not a ranking of company superiority, but an evidence maturity map. It helps distinguish three things often confused: companies possess adjacent capabilities, companies have completed glass samples, and companies have formed repeatable mass production. There are often several rounds of material—equipment—customer joint validations between the three.
VIII. Commercialization: How Long from Samples to HVM (High-Volume Manufacturing)?
Figure: Phased timeline of glass substrates from samples to HVM (High-Volume Manufacturing)
8.1 "2026 Corporate Goals" and "Around 2028 Industry Initial Production" Can Coexist
The 2026 report summary from SEMI and Global Net believes that glass core substrates can enter initial production for selective high-performance applications around 2028; its long-term CAGR scenario starts from an extremely low base and should not be understood as a near-term certain order growth rate. Companies proposing 2026 goals for samples, pilot production, or commercialization do not contradict this judgment, because samples, engineering lines, customer certification, low-volume manufacturing, selective initial production, and high-volume mass production are six different stages.
What is more worth observing in 2026—2027 is low-volume facilities, customer validation, and full-line closed-loops, rather than simply announcing "production line lighting up." Around 2028, if selective high-performance products see repeat orders and can publicly disclose panel-level yield, reliability, and equipment utilization, glass will move from a technical theme to commercial validation. Whether it can expand in 2029—2030 depends on the improvement speed of organic carriers, the cost of glass good area, terminal architecture adoption, and regional supply chain synergy.
8.2 Ten Leading Indicators More Useful Than Market Size Forecasts
First, whether terminals or OSATs explicitly define the role of glass in product-level BOMs, technical papers, or supplier certifications.
Second, whether substrate companies have shifted from sampling to repeat orders and disclosed the caliber of low-volume and HVM.
Third, whether raw sheets have semiconductor-grade bulk defect, TTV, and batch-to-batch consistency specifications.
Fourth, whether critical via defects are disclosed in ppm/dppm and full-panel electrical properties, rather than single-via percentages.
Fifth, whether there is data on large panel breakage rate, effective area, and yield.
Sixth, whether laser, wet, PVD/ECD, CMP, and inspection equipment have formed joint process windows and repeat acceptances.
Seventh, whether chemicals, targets, slurries, and dielectrics show regular consumption rather than one-time validation.
Eighth, whether reliability covers HAST, HTS, thermal cycling, copper diffusion, cracks, and delamination, and is traceable to process parameters.
Ninth, whether PDK, design rules, test structures, and multi-supplier standards are formed.
Tenth, whether the unit cost of good area decreases without sacrificing lifespan and rework.
IX. Conclusion: The True Inflection Point Is When Full-Panel Yield Enters a Verifiable Closed-Loop
The strategic significance of glass substrates is real. AI/HPC expands packaging size and I/O; HBM and Chiplet push up interconnect density; CPO brings optical links close to switching chips; and panel-level manufacturing requires more stable geometric baselines. Glass's low loss, dimensional stability, tunable CTE, flatness, and transparency provide a set of material solutions different from organic carriers and silicon interposers for these issues.
However, glass industrialization is not a straight line automatically deduced from "material advantages." Raw sheet defects determine the via formation window; via shape determines seed layer coverage; seed layer determines copper filling methods; copper volume determines thermal stress; and CMP and RDL amplify local defects into full-panel electrical and reliability issues. Inspection, software, PDK, and customer certification are not supporting links, but the manufacturing platform itself.
Therefore, researching glass substrates and TGV should adhere to three judgments. First, glass, organic, and silicon will coexist for a long time at different packaging levels and cost ranges, and the "comprehensive substitution" narrative should not be used in the short term. Second, the core of domestic substitution opportunities is not the expansion of equipment lists, but the stable windows, repeat orders, and good area costs run jointly by materials, equipment, substrates, and OSATs. Third, samples and low-volume manufacturing around 2026 are important progress, but the more decisive industry node is still whether verifiable initial production for selective high-performance applications can emerge around 2028.
The true inflection point for glass substrates is not a certain company drilling smaller vias, nor a certain production line lighting up for the first time; but when a large-area glass carrying hundreds of thousands or even millions of TGVs simultaneously meets via position, metallization, RDL, electrical properties, thermal cycling, breakage rate, and unit good area cost in continuous batches, and these results can be jointly audited by customers, equipment logs, and failure analysis. Only at that moment will glass transform from an "advanced packaging material hotspot" into a "scalable and replicable system platform."
References
1. Yole Group: Glass Materials for Advanced Packaging 2025.
2. SEMI × Global Net: Glass Core Substrate Market and Development Trends.
3. TrendForce: Glass Substrates Are Breaking Through the AI Chip Packaging Bottleneck.
4. Semiconductor Engineering / Onto: The Long Climb—Bringing TGV to High-Volume Manufacturing.
5. SCHMID Group: Any Layer ET for Full Panel-Level Advanced Packaging.
6. Counterpoint: FOPLP and Glass Substrate Forecast 2030.