【Related Companies】JNTC, Jinwoo Engineering (진우엔지니어링), COMET (코멧), TOPPAN, AST (Advanced Substrate Technologies), Philoptics, LPKF, Taesung (태성), SKC (Absolics), Samsung Electro-Mechanics, LG Innotek, Intel, TSMC, Ibiden, Unimicron, Innolux, TPK, AT&S, Shinko, Kinsus, BOE, WG Tech / Hubei TGVTECH, Lens Technology, Sky Semiconductor, 3D CHIPS (GUANGDONG) Technology, Fozhixin Microelectronics, MA-tek, etc.
I. Why Do AI Large Chips Require "2.0mm Ultra-Thick Glass Substrates"?
From 2025 to 2026, the demand for glass substrate thickness among top global semiconductor end customers has shifted significantly—rapidly moving from the early range of 0.8 to 1.1 mm to 1.5 to 2.0 mm or even thicker single-piece glass. The reason is that when panel-level packaging sizes expand to 510×515 mm and the number of Dies integrated per package increases exponentially, the glass core bears enormous asymmetric thermomechanical stress during the buildup of dozens of copper wiring and dielectric film layers on both sides (internal stress caused by CTE differences between glass, copper, and organic insulating films). Only by increasing the single glass substrate thickness to 2.0 mm (or evolving towards 3.0 mm in the next generation) can sufficient mechanical flexural rigidity be provided (flexural rigidity is proportional to the cube of thickness), thereby completely suppressing warpage and cracking of large panels during processing and service.
In this context, Glass Core Substrates, with their superior intrinsic physical and electrical properties, have officially moved from the laboratory to the forefront of industrialization.
In the complete process chain of glass substrates, back-end processing is the true technical deep water zone. Besides challenges such as laser modification, surface seed layer preparation, and plating uniformity, the most headache-inducing issue for the industry is structural damage caused by high-density opening. Due to the inherent brittleness of glass, the crack incidence rate increases exponentially during hole densification and extreme pitch shrinking. Balancing "high density" and "low breakage" has become the most urgent technical challenge today.
II. Why Is Traditional TGV Wet Plating So Slow?
However, doubling the glass thickness directly pushes the Through-Glass Via (TGV) metallization copper filling process to its engineering limits. Since glass itself is an insulator, thousands of micron-level vias must be drilled through 0.8 to 2.0 mm thick glass plates via laser-induced etching, and these holes must be filled defect-free with high-purity solid metal copper to achieve vertical electrical interconnection and efficient heat dissipation between the upper and lower surfaces.
In traditional processes, even completing pore-free, void-free solid copper filling for glass substrates with a thickness of 0.8 to 1.1 mm often requires half a day (12 hours) to a full day (more than 24 hours) using traditional wet electroplating. When the substrate thickness increases to 2.0 mm, the Aspect Ratio (ratio of hole depth to hole diameter) increases sharply, trapping traditional wet plating in a dilemma of being "slow as a snail with extremely high defect rates." Investigating the physical and electrochemical roots, this is primarily due to four core bottlenecks:
· Hydrodynamic and Mass Transport Bottleneck in Deep Holes: In vertical slender channels as thick as 0.8 to 2.0 mm with diameters of only tens of microns, convective exchange of plating solution is extremely weak. The replenishment of Cu2+ ions to the center depth relies mainly on slow concentration gradient diffusion. Once current density is blindly increased for speed, copper ions at the hole mouth grow preferentially and are instantly consumed, while the deep center falls into an "ion starvation" state due to severe concentration polarization.
· "Dog-boning" Effect and Internal Voids/Seams: Due to the high concentration of electric field lines at the openings of microvias (edge effect) and abundant copper ions, the copper deposition rate at the hole mouth is much faster than in the center. Both sides of the hole mouth thicken rapidly, forming protrusions resembling "dog bones," pinching off the hole mouth prematurely and sealing the unfilled center, leaving fatal voids or axial seams inside the glass substrate (MA-tek, https://www.matek.com/techarticle-detail/90/). During subsequent reflow soldering at hundreds of degrees Celsius or high-load chip operation, residual plating solution and gas within sealed voids expand violently upon heating, easily causing burst holes, copper pillar fractures, or high-impedance failures.
· Strict Time Window for Ternary Organic Additive Synergy: To avoid premature pinch-off, traditional straight vias are forced to adopt the "Butterfly Filling (BFT)" strategy—using precise ratios of suppressors (e.g., PEG macromolecules adsorbing on hole walls to reduce overpotential), levelers (e.g., PVP blocking tip growth), and accelerators (e.g., SPS small molecules concentrating in the center to promote deposition)—to allow copper to grow laterally from the exact center first and bridge (resembling butterfly wings), then grow towards the top and bottom. However, this electrochemical dynamic equilibrium is extremely fragile, requiring low current densities and long pulse periods to slowly incubate, taking 12 to 24 hours, severely locking the daily throughput of each plating machine.
· Weak Adhesion at Copper-Glass Interface and Surface Dimpling: Silicon wafer surfaces are rough and processes are mature, whereas glass surfaces are atomically smooth with strong chemical inertness, resulting in poor natural adhesion to metal copper, making delamination, bulging, or curling prone (KIPOST, https://www.kipost.net/news/articleView.html?idxno=325957). Additionally, when via filling ends, the center of the hole mouth is often lower than the surrounding surface, forming dimple defects. This not only disrupts the depth of focus for subsequent RDL fine-line lithography but also incurs high consumable costs and risks of glass micro-cracks if heavy Chemical Mechanical Polishing (CMP) is used to force flattening.
III. Deep Dive into JNTC's Dual Codes for "Minutes-Level" Copper Filling
On October 6, 2026, according to reports by South Korea's authoritative semiconductor media outlet The Elec, JNTC (제이앤티씨, Stock Code: 204270.KQ), a leading Korean enterprise in electronic core components and glass processing, officially announced it had overcome this core hurdle plaguing the global packaging community: reducing the time required for complete, defect-free solid copper filling on a single TGV glass substrate sized 510×515 mm and 2.0 mm thick from half a day to a full day down to "minutes," with a mass production comprehensive yield of approximately 94%. Notably, this 2.0 mm product is processed directly from a single intact piece of 2.0 mm thick glass, rather than the "two pieces of 1.0 mm glass laminated" compromise adopted by some industry players to evade deep-hole plating difficulties.
Based on public technical data and electrochemical deposition principles, JNTC achieved a copper filling efficiency leap of over 100 times by establishing a dual physicochemical closed loop of "Hourglass Via Geometric Reconstruction" and "Proprietary Metallization New Process":
First Code: Hourglass (X-shaped) Microvia Geometry—Transforming "Deep Straight Vias" into "Dual Symmetric Shallow Blind Vias"
As shown in Figure 1, traditional vertical vias have consistent diameters top-to-bottom, resulting in extremely long mass transport paths for plating solution in a 2.0 mm deep cylinder. JNTC utilizes double-sided precision laser modification combined with controlled wet chemical etching to precisely shape the vias within 2.0 mm glass into an "Hourglass / X-shaped Via" structure (narrow in the middle, wide at both ends). This geometric innovation brings three significant gains in fluid dynamics, electrochemistry, and structural mechanics:
· 1. Instant Waist Bridging: Since the "Waist" in the exact center of the hourglass via has the narrowest diameter, when metallization deposition starts, the copper plating on both sides of the narrow waist needs to grow only a very short distance to meet and seal in the center (Bridge). The originally long and difficult-to-control "butterfly incubation phase" of straight holes is completed instantly by the geometric narrowing effect (Abang Semiconductor Network, https://www.ab-sm.com/a/71098).
· 2. Transformation into Dual Symmetric V-Shaped Shallow Blind Vias, Enabling High-Current Bottom-Up Rapid Filling: Once the waist bridges and seals in an extremely short time, the original single high-aspect-ratio via 2.0 mm deep physically transforms immediately into two symmetric V-shaped conical blind vias, each halved in depth (approx. 1.0 mm) and open outwards (Abang Semiconductor Network). The open conical bell mouths completely eliminate dead zones for mass transport in deep holes, allowing high-speed flushing and replacement of plating solution; simultaneously, accelerators naturally concentrate at the narrow V-shaped hole bottoms (the hourglass waist bridging point), while suppressors distribute across the wide hole mouths, enabling the application of current densities several to tens of times higher than traditional butterfly plating. This achieves rapid solid growth from the center towards both ends (Bottom-up), fundamentally eliminating the generation of central voids and seams (Abang Semiconductor Network).
· 3. "Bidirectional Mechanical Rivet" Locking Effect: Since the thermal expansion coefficient of glass (~3.8 ppm/K) is far lower than that of metal copper (~16.5 ppm/K), solid copper pillars in straight cylindrical holes are prone to axial slippage, protrusion (Copper Pumping), or even detachment during high-low temperature cycles. JNTC's hourglass vias, being wide at the top and bottom and narrow in the middle, form symmetrical conical wedges after solid copper fills and cures, gripping the glass body firmly from both sides like a double-headed mechanical rivet, eliminating risks of copper pillar slippage and detachment.
Second Code: Proprietary High-Adhesion Metallization and "CMP-Free" Flattening Suppression Technology
Beyond the hourglass via geometry, JNTC's second major breakthrough is its highly confidential proprietary metallization process. According to technical parameters disclosed on JNTC's official website, its metallization system achieved breakthroughs in three dimensions:
· Ultra-High Interface Adhesion Strength (Adhesion > 500 gf/mm): Addressing the pain point of copper plating difficulty on smooth glass surfaces, JNTC achieved nanometer-scale uniform hole wall micro-roughening and low-damage modification during the laser modification and precision wet etching stages. Combined with high-density Seed Layer deposition technology, the Peel Strength between the copper plating and the glass substrate exceeded 500 gf/mm (JNTC Official Website), ensuring no delamination occurs in high-stress buildup layers on 2.0 mm thick boards.
· Complete Elimination of Surface Dimpling (Dimple-free) and Voids (Void-free): Through proprietary plating bath chemical formulations and flow-field-electric-field coupling control, when copper rapidly fills from the hourglass waist towards both ends up to the hole mouth plane, the system accurately suppresses overburden at the hole mouth and automatically levels the center, eliminating the Dimple effect that has troubled the industry (The Elec).
· Moving Towards "CMP-Free" or Minimal Flattening Processes: JNTC's official technology roadmap explicitly lists "CMP-free: achieving uniform plating thickness, simplifying process flows, and significantly reducing manufacturing costs" as a technical feature (JNTC Official Website). Combined with Advanced Packaging Failure Analysis (FA) standards from MA-tek (https://www.matek.com/techarticle-detail/90/), including 2D/3D X-ray non-destructive array scanning, White Light Interferometry (WLI) surface morphology measurement, Scanning Electron Microscopy (SEM) targeted cross-section inspection, and Electron Backscatter Diffraction (EBSD) copper grain orientation analysis, JNTC's 2.0 mm TGV glass substrates passed rigorous verification regarding intra-hole crystalline density, zero porosity, and surface flatness (The Elec).
IV. Commercial Closed Loop from Equipment Self-Development to KRW 347 Billion Capacity Expansion
In semiconductor manufacturing, there is often a huge gap between running samples in the lab and stable mass production in factories. Why can many laser equipment makers drill holes in 2.0 mm glass but fail to achieve mass-production-grade copper filling? JNTC's answer is: Vertical Integration from core equipment design to full-process technology.
Full Chain Internalization of Equipment and Process: The Moat of "Never Selling Core Equipment Externally"
JNTC officially entered the semiconductor glass substrate track in 2024 and quickly completed its vertical integration layout:
· Parent Company Equipment Gene Support: Except for some standard Automated Optical Inspection (AOI) equipment, all core machines in JNTC's entire chain of "Cleaning → Laser Processing → Etching → Solid Metallization → CMP" are independently developed and manufactured by its controlling parent company and automation equipment manufacturer, Jinwoo Engineering (진우엔지니어링, JNTE) (The Elec).
· Absorbing COMET for Precision Plating and Etching Expertise: In 2025, JNTC formally absorbed and merged its subsidiary COMET (코멧), which specializes in precision plating and chemical etching processes, injecting over thirty years of wet chemistry experience accumulated in consumer electronics 3D curved glass processing and precision connector plating into the TGV process (The Elec Korea).
· Strict Ban on External Sales of Core Equipment: JNTC officially stated that since the core process parameters for "minutes-level filling" and "hourglass via formation" are deeply embedded in the mechanical structures, flow chambers, and control algorithms of its self-developed equipment, JNTC will never sell any core machines externally, even if external customers request them, thereby building a technical barrier against reverse engineering (The Elec).
Top Customer Verification and KRW 347 Billion Capacity Blueprint
Leveraging the cost and delivery advantages brought by minutes-level copper filling, JNTC's commercialization process is accelerating:
· Joint Verification by US, Japan, and Taiwan Giants: In June 2026, JNTC pioneered the development of 2.0 mm thick TGV glass substrates and successfully passed quality verification by a US semiconductor end customer (market consensus points to AI ASIC and network chip leader Broadcom) and mass production efficiency verification by Japanese packaging substrate giant TOPPAN. In July 2026, JNTC, along with Broadcom and TOPPAN, signed a Memorandum of Understanding (MOU) for commercial cooperation with AST (Advanced Substrate Technologies), a joint venture established in Singapore. AST's first advanced FC-BGA and substrate factory in Singapore was officially commissioned on September 29, 2026 (Anue鉅亨網). Additionally, JNTC is advancing 2.0 mm product verification with a Chinese Taiwan-based end customer and has been invited by another US Big Tech company to conduct in-depth technical collaboration at its US headquarters.
· 27 NDAs and Paid Sample Conversion: As of October 2026, JNTC has signed Non-Disclosure Agreements (NDAs) with 27 global companies covering chip designers/IDMs, OSATs, and packaging substrate manufacturers (7 of whom are end-chip demand parties). Seven core customers have transitioned from free sample testing to the "Paid Samples" stage to advance subsequent Buildup process verification (The Elec). Meanwhile, JNTC has achieved coverage of the full thickness product line from 0.3 mm to 2.0 mm and is developing 3.0 mm ultra-thick glass substrates.
· Hwaseong Pilot Line and Gimcheon KRW 347 Billion Mass Production Base: Currently, JNTC operates one TGV pilot line (Pilot Line) in the former COMET facility within the Mado Industrial Park in Hwaseong City, Gyeonggi Province, South Korea, with a monthly capacity of 10,000 to 12,000 large panels. It plans to officially start commercial mass production supply of 2.0 mm glass cores in 2027 (The Elec). To meet commercial demand post-2028, JNTC signed an investment MOU with North Gyeongsang Province and Gimcheon City in September 2026, committing to invest KRW 347 billion (approx. USD 255 million) before 2030 to build a large-scale glass substrate mass production base on approximately 30,000 pyeong (approx. 99,000 square meters) of land in Gimcheon City. Construction is scheduled to begin in the second half of 2027, initially building 2 to 3 lines to connect with commercial volume ramp-up in mid-2028, with long-term expansion to more than 10 high-speed lines.
· Pioneering the "Glass Substrate Foundry" Model: JNTC does not compete with downstream substrate factories for RDL buildup business but positions itself as a universal "Glass-Core Foundry" globally. Whether vendors who have formed their own equipment alliances or substrate/OSAT manufacturers lacking front-end laser etching and copper filling capabilities, they can customize circuit patterns, via diameters, pitches, glass thickness, and copper plating thickness based on JNTC's services. They can even modularly outsource specific steps from cleaning, laser drilling, etching, copper filling/metallization to CMP, while focusing themselves on Buildup processes (The Elec).
V. The 2.0 mm Era Begins: Who Will Dominate Next-Generation Advanced Packaging?
JNTC's "minutes-level copper filling" caused a sensation in the industry because it directly broke the most critical capacity bottleneck in the current global race for 2.0 mm thick glass substrates. Looking at the global supply chain, the competition around TGV glass substrates has diverged into two dimensions: the first is the "race for 2.0 mm ultra-thick glass microvia processing and copper filling speed," and the second is the "global full-stack glass substrate giants' mass production positioning battle."
Dimension One: First-Mover Camp Comparison for 2.0 mm Thick Glass Substrates—"Drilling Holes" Does Not Equal "Fast Copper Filling"
At the Korea International Circuit Assembly & Packaging Show (KPCA Show 2026) held in September 2026 and recent industry developments, multiple international equipment vendors showcased results for 2.0 mm glass substrates. However, as quoted by The Elec from industry insiders: Apart from JNTC, most vendors have currently only solved the "Microvia Drilling" problem, while still failing to break through the key "defect-free high-speed copper filling" step.
Dimension Two: Global Glass Substrate Full Industry Chain Giant Race Landscape (Korea, US, Japan, Taiwan, Europe)
Beyond upstream TGV glass cores and equipment breakthroughs, global semiconductor IDMs, substrate giants, and display panel enterprises are also pushing forward the commercial implementation of glass substrates:
Through the above global comparison, it can be seen that international leaders are targeting trial production in 2026 and mass production ramp-up in 2027–2029. JNTC avoids direct competition with Samsung Electro-Mechanics, Unimicron, Ibiden, and TOPPAN in back-end high-density buildup, instead positioning itself in the unavoidable "2.0 mm thick board TGV high-speed drilling and minutes-level solid copper filling" segment. As JNTC executives stated, even enterprises that have already united multiple equipment and material suppliers to build their own glass substrate lines now tend to outsource the time-consuming and yield-controlling "TGV hole formation and copper filling metallization" to JNTC, concentrating their own resources on back-end circuit buildup. Overall, the domestic industry is transitioning from technology R&D and pilot validation to commercial delivery, with domestic players like BOE, WG Tech, and Lens Technology having completed board-level process integration.
VI. Summary and Industry Implications
When AI computing power chips drive glass substrates from 0.8 mm to 2.0 mm ultra-thick specifications, the traditional wet plating cycle of 12 to 24 hours for copper filling was once considered the main bottleneck hindering large-scale commercialization of glass substrates in 2027.
Through the synergy of "Hourglass Via Geometric Structure Design" and "Self-Developed High-Adhesion Defect-Free Metallization Process," JNTC not only transformed the deep-hole mass transport challenge into dual-symmetric shallow V-hole high-speed Bottom-up growth in physical mechanisms, achieving an efficiency leap from "day-counted" to "minutes-level," but also resolved the reliability pain points of ultra-thick glass substrates with bidirectional rivet anchoring structures and a 94% yield. This breakthrough offers three implications for the global and local semiconductor advanced packaging supply chains:
· 1. Structural Innovation and Electrochemical Processes Must Be Deeply Coupled: Simply improving plating bath additive formulations is difficult to cope with the aspect ratio limits of 2.0 mm or even 3.0 mm ultra-thick glass. Only by holistically designing front-end laser modification and etching hole shapes (such as controlled taper of hourglass/X-vias) with back-end electrochemical fluid mass transport can a leap in mass production rhythm be achieved.
· 2. Vertical Internalization of "Equipment + Process + Materials" Is a Key Guarantee for Process Moats: Relying on parent company Jinwoo Engineering's self-developed equipment and absorbing COMET's internalized plating processes, JNTC achieved full closed-loop control from cleaning, laser, etching, and copper filling to CMP. This strategy of "process固化 in self-developed equipment and no external sales" significantly shortened the online yield ramp-up period.
· 3. "Glass Core Board Foundry Outsourcing" Will Become a New Division of Labor Model in Advanced Packaging: With international companies like Broadcom and TOPPAN (AST) being the first to verify and introduce specialized TGV glass core board foundry services, the future glass substrate industry is expected to form a division of labor pattern of "Front-end TGV Core Specialized Foundry + Back-end RDL Buildup Custom Packaging." Enterprises that first master high-efficiency, low-cost, thick-board defect-free copper filling capabilities will occupy key positions in the next-generation AI computing power infrastructure supply chain.
References:
1. Selye Moon, "JNTC Cuts TGV Copper Filling Time to Minutes — Company completes US big-tech validation and plans mass production of glass cores in 2027", The Elec Inc., 2026-10-06. https://www.thelec.net/news/articleView.html?idxno=14434
2. 문세려 (Selye Moon), "12시간을 분 단위 단축…제이앤티씨, 유리기판 충진기술 개발", 디일렉 (The Elec Korea), 2026-10-06. https://www.thelec.kr/news/articleView.html?idxno=63298
3. 庄闵棻 编译, "玻璃基板大突破！南韓JNTC將填銅時間從1天縮至數分鐘、良率達94%、2027年拚量產", Anue鉅亨網, 2026-10-11. https://news.cnyes.com/news/id/6627513
4. 數位時代 (Business Next), "玻璃基板技術大突破！韓廠攻克TGV銅填充瓶頸，欣興、群創等台廠進度如何？", 數位時代, 2026-10-08. https://www.bnext.com.tw/article/92573/jntc-tgv-glass-substrate-copper-filling
5. 財報狗 (StatementDog), "韓廠JNTC 攻下玻璃基板新技術力拚2027 年量產、博通傳為潛在客戶", 財報狗新聞, 2026-10-08. https://statementdog.com/news/17853