[Relevant Companies Involved in This Article] SK hynix, Samsung Electronics, Micron Technology, TSMC (Taiwan Semiconductor Manufacturing Company), ASE, Amkor, Intel Foundry, PTI, Kaifa Technology/Payton, Taiji Industry/Haitai/Taiji Semiconductor, Hua Tian Technology, TFME, Longsys/Yuancheng Suzhou, Biwin Storage/Xingcheng Hanqi/Huizhou Biwin, DMET, Huicheng Electronics / Xinfeng Technology, YMTC, CXMT, SJ Semiconductor, JCET, USI Electronics, Tiancheng Advanced, WY Semiconductor, Shandong Xinhengguang, Shenzhen Memory Technology, Jingwang Semiconductor (Shandong), etc.
I. Industry Overview: Two Technical Mainlines of Conventional Memory Packaging and HBM
Concept confusion is particularly prevalent in memory packaging: a company possessing TSV, bumping, or 2.5D capabilities does not equate to having the qualification for mass production of HBM stacks; similarly, a company capable of packaging DDR5 does not necessarily mean it can undertake system-level integration between GPUs and multiple HBM chips.
Figure 1 Global Memory Packaging Company Role Matrix (Conservatively graded in this article based on public data)
Data Sources: Company annual reports, official technical materials, exchange filings, and original articles.
SEMI, citing Yole's industry judgment, indicates that global advanced packaging revenue is expected to grow from $46.1 billion in 2024 to $79.4 billion by 2030. Meanwhile, in its 2026 public forecast, SEMI pointed out that HBM and DDR5 demand is driving a significant increase in DRAM equipment investment. These two trends illustrate that memory packaging, on the one hand, accommodates the massive demand from traditional servers, smartphones, automotive, and consumer electronics, and on the other hand, is being redefined by the extreme requirements for bandwidth and energy efficiency from AI accelerators.
Figure 2 Two Engineering Routes for Conventional Memory Packaging and HBM Packaging
Data Sources: Corporate technical materials and public industry information.
Conventional memory packaging and HBM correspond to two complementary, rather than simply substitutive, engineering routes: the former covers a wide range of products including server DRAM, LPDDR, eMMC, UFS, uMCP/eMCP, SSD dies and modules, with the core focusing on ultra-thin die processing, multi-die stacking, wire loop height control, flip-chip and wire-bond hybrid packaging, molding compound warpage control, and high-speed test procedures. Its commercial value is mainly reflected in economies of scale, customer stickiness, and long-term cash flow. The latter must be divided into two stages: "stack manufacturing" and "system integration." The front-end is completed by memory IDMs on DRAM wafers, involving TSV, thinning, KGD screening, and multi-layer stacking. The back-end then integrates the finished HBM stacks with GPUs, ASICs, or CPUs onto silicon interposers, bridge chips, or high-density fan-out platforms. Therefore, its barriers are concentrated in high-precision alignment, thermal compression windows, material formulations, in-line inspection, KGD, and system-level yield coordination.
Why "Knowing How to Do TSV" Still Does Not Equal "Knowing How to Do HBM"
HBM is a typical multiplicative yield product. An HBM stack contains multiple high-value DRAM dies, and any defect in a single layer can lead to the scrapping of the entire stack. When the HBM is further integrated with the GPU and interposer, the system-level yield is further amplified by the interposer, micro-bumps, substrate, and assembly processes. Therefore, companies that can truly achieve mass production must simultaneously possess capabilities in high-precision alignment, void control, warpage control, thermal compression window management, material formulations, in-line inspection, KGD, and final testing. This is why there are many companies in the public market that "possess a certain process," while very few can stably supply HBM.
Figure 3 Multi-Stage Yield Model of the HBM Value Chain (Drawn in this article)
Data Sources: Compiled based on public technical processes for HBM manufacturing and 2.5D packaging.
II. International Companies: The Big Three in HBM and System-Level Packaging Platforms
2.1 SK hynix: Leader in HBM Stack Mass Production, MR-MUF Forms a Process Moat
SK hynix is currently the most representative "memory device + stack packaging" integrated company in the HBM industry chain. Its MR-MUF route improves heat dissipation, mechanical stability, and multi-layer stacking efficiency by injecting molded underfill material after stacking, and has been extended to Advanced MR-MUF. In 2024, the company took the lead in promoting the mass production of 12-layer HBM3E, and will continue to advance HBM4 and HBM4E samples and mass production preparation from 2025 to 2026. SK hynix's advantage lies not only in the packaging process itself but also in the full-chain coordination of DRAM front-end, packaging materials, testing, and customer certification.
In its regional layout in China, the Chongqing DRAM back-end base is an important node for memory packaging in the central and western regions; in Wuxi, SK hynix has formed long-term back-end process coordination through Haitai Semiconductor. This indicates that the packaging network of international memory IDMs is not concentrated in a single country but is organized through front-end fabs, dedicated back-end facilities, joint-venture OSATs, and system-level packaging partners.
2.2 Samsung: TC-NCF, HBM4, and Foundry Synergy, Aiming to Rebuild Market Share
Samsung's route emphasizes TC-NCF thermal compression bonding and intra-group foundry synergy. HBM4 begins to introduce more complex logic base dies, making the interface between memory devices, advanced logic processes, and packaging even tighter. Samsung publicly announced the commercial shipment of HBM4 in 2026 and is advancing HBM4E samples. Its competitive focus has shifted from simply stacking layers to data rate, power consumption, thermal stability, and customer customization.
Samsung's uniqueness lies in simultaneously possessing the DRAM, foundry, packaging, and substrate/electronic materials ecosystem. Therefore, theoretically, it can shorten the joint optimization cycle between the HBM logic base die and the memory stack. However, whether intra-group synergy can be translated into stable yields and customer share still depends on long-term validation, not just a single sample metric.
2.3 Micron: Entering the New Generation AI Platform with HBM4 Mass Production
Micron is the relatively smaller but faster-attacking player among the Big Three in HBM. In 2026, the company announced that HBM4 has entered high-volume mass production to serve the new generation AI platform, while simultaneously advancing 16-layer 48GB samples. Micron's strategy is to combine advanced DRAM nodes, logic base dies, stack packaging, and the U.S. domestic supply chain narrative to expand its share by leveraging customer platform upgrades.
From the perspective of competitive logic, the HBM market does not only look at absolute capacity. For AI chip customers, the more qualified suppliers there are, the lower the supply risk. Therefore, even if Micron's share is not as large as SK hynix's, as long as it can complete certification on key platforms, it can secure high-value orders and influence the overall HBM pricing and technological pace.
2.4 TSMC (Taiwan Semiconductor Manufacturing Company): Does Not Produce HBM, but Controls the Key Entry Point for GPU+HBM System Integration
TSMC's CoWoS-S, CoWoS-L, and other platforms interconnect logic chips and multiple HBMs through silicon interposers or local silicon bridges with high density. Its commercial value lies not in manufacturing memory dies, but in mastering the process design rules, capacity scheduling, and customer coordination for the final packaging body of AI accelerators. As the packaging body size expands, CoWoS capacity once became a critical constraint on AI chip shipments, indicating that advanced packaging has transformed from a back-end service into system capacity.
2.5 ASE and Amkor: OSATs Moving Up to 2.5D/HBM System-Level Integration
ASE connects SoCs and HBMs through platforms such as VIPack, FOCoS-CL, and FOCoS-Bridge, attempting to reduce the cost of full-size silicon interposers with fan-out, bridge, and panel-level processes. Amkor has long provided 2.5D TSV, HDFO, and high-end testing services, explicitly targeting AI/ML chips and HBM integration. The common direction for both companies is: upgrading from packaging manufacturing contractors to heterogeneous system integrators, seizing higher-value segments with design, thermal simulation, substrates, testing, and mass production services.
2.6 PTI: One of the Strongest Professional Players in Conventional Memory Packaging, While Layout HBM
PowerTech Technology Inc. (PTI) is an indispensable international professional memory OSAT in this article. Its public data covers a wide range of categories including TSOP, MCP, wBGA/FBGA, SD, microSD, USB, SSD, eMMC, eMCP, UFS, and DRAM stacking, and it continues to develop TSV, NCF, and high-density HBM-related technologies. PTI's advantage lies in its broad memory product spectrum, deep mass production experience, and long-term cooperation with memory IDMs; its challenge is that HBM system-level integration requires larger capital expenditures and deeper synergy with logic chip customers.
2.7 Intel Foundry: Participating in HBM System Packaging with EMIB and Foveros
Intel is not a memory packaging company, but its EMIB, Foveros, and hybrid bonding platforms can combine compute chiplets, I/O dies, and HBM into high-performance systems. In the HBM4 era, with enhanced customization of logic base dies, the boundaries between CPU/GPU design, advanced logic manufacturing, and packaging are further blurred. Intel's value lies in co-optimizing architecture design and packaging. Therefore, Intel should be classified as an "HBM system integration platform" rather than an "HBM stack manufacturer."
III. Chinese Companies: From DDR/NAND Mass Production Base to HBM Platform Breakthrough
Chinese memory packaging enterprises are not in a single tier. The first category consists of professional back-end companies that have already formed large-scale mass production of DDR, NAND, UFS, eMMC, etc.; the second category involves memory product companies vertically integrating into the packaging and testing segment; the third category focuses on 2.5D/3D, TSV, and hybrid bonding platforms, mainly competing for HBM system-level integration or next-generation stacking opportunities. When analyzing, cash flow capability, capacity scale, customer certification, and technological foresight must be evaluated separately. In addition, YMTC (Yangtze Memory Technologies Corp) and CXMT (ChangXin Memory Technologies) represent NAND and DRAM IDMs respectively, and their value lies in driving the coordination of packaging, testing, and modules from the device definition end. DMET represents an asset-light back-end coordination model of "product definition, in-house controller/firmware and testing, with packaging mainly outsourced," which should be evaluated differently from companies that build complete in-house packaging lines.
Figure 4 Public Maturity Ladder of Chinese Enterprises in Memory Packaging (Drawn in this article)
Data Sources: Conservatively graded based on company announcements, annual reports, exchange audit documents, and original articles.
3.1 Kaifa Technology/Payton: Core Mass Production Platform for Domestic Conventional Memory Packaging and Testing
Shenzhen Payton and Hefei Payton, under Kaifa Technology, are among the most scaled memory packaging and testing enterprises in China. The company's public data covers DDR4/DDR5, LPDDR4/LPDDR5, NAND SSD dies, uMCP, UFS, and other products, and possesses wBGA, FBGA, multi-layer stacking, and supporting test software capabilities. In 2026, relevant expansion plans continue to be directed towards memory packaging and testing capacity.
Payton's competitive advantage lies in its mass production synergy with domestic memory customers, product variety, and test program accumulation. Its HBM value is more appropriately described as a "reserve platform extending from high-end DDR and multi-die stacking to TSV/high-bandwidth memory," rather than a publicly confirmed large-scale HBM supplier. In the short term, the company's most certain benefits still come from DDR5, LPDDR5, UFS, and NAND product upgrades.
3.2 Taiji Industry/Haitai Semiconductor: Underestimated High-Layer DRAM/NAND Back-End Capabilities
Taiji Industry conducts memory packaging and testing through Haitai Semiconductor and Taiji Semiconductor. Haitai has long provided back-end process services for SK hynix's DRAM, while Taiji Semiconductor expands DRAM and NAND overall solutions among market-oriented customers. The 2025 semi-annual report disclosed that Haitai's packaging and packaging & testing maximum monthly output reached 2.39 billion Gb and 2.58 billion Gb, respectively; Taiji Semiconductor achieved mass production of 16D high-stack products, a breakthrough in 32D technology, and completed the validation and mass production of 1β DRAM and 300+ layer NAND.
Such capabilities are critical for the upgrading of China's memory packaging. It proves that domestic back-end platforms are no longer limited to traditional single-die BGA but can handle ultra-thin dies, high-layer stacking, and advanced node memory. Although this is still different from HBM's TSV stack, it has obvious technical migration value in thinning, stacking, materials, and testing.
3.3 Hua Tian Technology: Strengthening High-End Memory Full Process with Nanjing Project
Hua Tian Technology has formed a multi-location layout in Tianshui, Xi'an, and Nanjing. The second phase, second stage of the Nanjing Advanced Packaging and Testing Base project involves an investment of about 3 billion RMB. Public announcements clearly state the construction of a full process for memory IC packaging and testing, with a planned annual packaging and testing volume of about 430 million units upon reaching full capacity. Original articles further identify eSiFO, eSinC, and 3D DRAM stacking as Hua Tian's technical mainlines, indicating that the company is extending from BGA/FBGA scale packaging to silicon-based fan-out, TSV, and 3D memory.
Hua Tian's advantages are its comprehensive OSAT capabilities, customer coverage, and multi-base synergy; the challenge is translating technology platforms into stable yields for high-end memory. Its evaluation should be divided into two layers: the expansion of conventional and high-end memory packaging and testing is a confirmed fact, while HBM-level 3D DRAM mass production still awaits more specific customer and product disclosures.
3.4 TFME (Tongfu Microelectronics): Dual Lines of Memory Expansion and 2.5D System Integration
TFME's Hefei project is explicitly targeted at FLASH, DRAM, and other memory chip packaging and testing, with about 800 million RMB in the private placement project used for capacity enhancement in memory chip packaging and testing. Meanwhile, TFME's VISionS platform can connect compute dies and multiple HBMs using silicon interposers, TSV, and micro-bumps, enabling the company to possess two growth logics: "conventional memory packaging and testing expansion" and "HBM system-level integration platform." [16]
TFME's core assets are its long-term cooperation with high-performance computing customers and large-scale FC/2.5D engineering experience. However, in the HBM segment, its role is closer to integrating external HBM stacks with compute chips, rather than independently manufacturing HBM DRAM stacks. Future value depends on 2.5D product yields, customer platform share, and the capacity utilization rate of the Hefei memory project.
3.5 Longsys/Yuancheng Suzhou: Vertical Integration from Memory Product Definition to Advanced Packaging and Testing
Longsys established WLP, SiP, wBGA, FBGA, FCBGA, FCCSP, and ultra-thin die stacking capabilities by acquiring the former Force Cheng Suzhou and renaming it Yuancheng Suzhou, forming an integrated chain of "memory product R&D—packaging and testing—modules—brand/industry customers." The advantage of this model is that packaging capabilities directly serve self-developed products while opening capacity to external customers, shortening the validation cycle for new products.
In the upgrading of AI edge and enterprise storage, packaging is not just a manufacturing cost but also determines product thickness, capacity, bandwidth, and power consumption. Longsys's opportunities lie in ePOP, UFS, enterprise SSDs, and high-end memory products; its realistic path to extend into HBM is more likely to first go through high-density SiP, FCBGA, and compute-storage collaborative packaging, rather than directly stepping into HBM stack manufacturing.
3.6 Biwin Storage/Xingcheng Hanqi/Huizhou Biwin: Industrialization Validation of FOMS and Wafer-Level Advanced Packaging
Biwin Storage has laid out the Xingcheng Hanqi wafer-level advanced packaging and testing project in Songshan Lake, Dongguan. Public annual reports disclose capabilities in thinning, RDL, bumping, underfill, molding, and substrate mounting, and propose the FOMS (Fan-Out Memory Stacking) and heterogeneous integration direction; Huizhou Biwin undertakes the expansion of advanced packaging and testing for memory chips. The company is close to AI terminals and memory product definition ends, possessing the advantage of quickly introducing packaging into products.
It must be emphasized that FOMS, TSV, RDL, and bumping are necessary capabilities for entering high-end memory packaging, but they do not automatically equal HBM mass production. Biwin's current stage is more appropriately defined as "advanced memory packaging validation, capacity ramp-up, and compute-storage co-packaging cooperation introduction." If the project can form stable external customers and yield data, its value will elevate from internal manufacturing capability enhancement to an independent advanced packaging platform.
3.7 DMET: Integration of Memory Products, Controllers, and Testing, with Packaging Mainly Outsourced to Professionals
DMET is a representative domestic memory controller chip and memory product company, with products covering solid-state drives, embedded storage, memory modules, and mobile storage. Public products include DDR5 U-DIMM/SO-DIMM, LPDDR5/5X, eMMC, UFS, and SSD. The company's 2025 annual report shows that the Futian Intelligent Manufacturing Memory Product Industrial Base has established a DIE chip testing line, with memory wafer sorting and testing mainly completed by its own production lines; simultaneously, a BGA packaging substrate testing line has been established to conduct independent testing on some packaging semi-finished products.
From the perspective of the packaging model, DMET's wafer die packaging and memory module packaging are still mainly entrusted to professional packaging and testing companies: the company provides core materials such as NAND Flash wafers and flash memory controller chips to outsourced manufacturers, who complete TSOP/BGA die packaging or memory module packaging. Therefore, its accurate positioning is not an independent OSAT, but a memory product integration platform of "product definition + in-house controller/firmware + in-house DIE/BGA testing + outsourced packaging." The company's 2025 refinancing plan plans to invest in SSD expansion and DRAM memory product expansion. If the project is successfully implemented, it will further amplify its demand for outsourced packaging, testing, and module manufacturing capabilities. However, as of the data cutoff date of this article, there is no public information proving its mass production capability for HBM stacks or 2.5D HBM system-level packaging.
3.8 YMTC: Integration of 3D NAND Design, Manufacturing, Packaging/Testing, and System Solutions
YMTC is a typical IDM-style platform in China's memory industry. Its official website explicitly covers 3D NAND design, manufacturing, packaging and testing, and system solutions, with products extending to eMMC, UFS, and SSD. Its packaging value lies not only in back-end capacity but also in the ability to co-optimize NAND layers, die specifications, controllers, packaging, and modules.
YMTC is not an HBM company, but its existence provides a real and continuous memory packaging demand scenario for Wuhan and the central and western regions, and also promotes the formation of local testing, materials, equipment, and advanced packaging platforms. From the perspective of industrial security, full-chain NAND capabilities are as important as HBM, especially in the context of AI data centers driving the growth of enterprise SSD demand.
3.9 CXMT: DDR5 Mass Production Base of Domestic DRAM IDM and Potential HBM Synergy Entry Point
CXMT is a representative DRAM integrated memory manufacturing company in mainland China, with business covering DRAM design, R&D, production, and sales. The company's official website has publicly released DDR5 and module products, with die maximum speeds reaching 8000Mbps, capacity covering 16Gb/24Gb, and layout for LPDDR5/5X and other products, targeting servers, high-performance computers, and mobile terminals. For the memory packaging industry, CXMT's core value is not acting as an independent OSAT to undertake external orders, but providing domestic DRAM dies, product definitions, testing specifications, and scale demand, serving as an important demand anchor for the domestic DDR5 packaging and module ecosystem.
CXMT should be distinguished from YMTC: the former focuses on DRAM, while the latter focuses on 3D NAND. Regarding HBM, as of the data cutoff date of this article, formal public information such as the company's official website has not confirmed that HBM stacks have achieved large-scale mass production. Therefore, this article positions it as "mature mass production of conventional DRAM + potential participant in HBM packaging synergy," and does not parallel it with the HBM mass production status of SK hynix, Samsung, and Micron. Future observation focuses on whether TSV DRAM, KGD, stacking, and testing capabilities form formal product disclosures, as well as the progress of joint validation with domestic AI chips and advanced packaging platforms.
3.10 SJ Semiconductor: SmartPoser Represents China's Leading Platform for 2.5D/HBM System Integration
SJ Semiconductor's SmartPoser implements 2.5D silicon interposers and multi-chip integration based on a 12-inch wafer-level platform. Exchange filing documents show that platforms such as SmartPoser-POP have entered large-scale mass production, and the company's revenue is growing rapidly. Original articles classify it as a 2.5D delivery platform for memory and AI customers, which is one of the more realistic routes for Chinese enterprises in the direction of HBM system-level integration.
SJ Semiconductor's positioning is close to "middle-end manufacturing + advanced packaging platform." Its competitors are not only traditional OSATs but also the advanced packaging departments of foundries. Future core observation indicators are customer concentration, product yield, testing capabilities, and the capacity ramp-up of the Lingang 3DIC project.
3.11 JCET: XDFOI and Lingang Project Target High Computing Power and High-Bandwidth Memory
JCET's XDFOI achieves 2D, 2.5D, and 3D heterogeneous integration through high-density RDL, emphasizing reducing reliance on full-size silicon interposers. Original articles summarize the direction of the Lingang advanced packaging base as 2.5D/3D, HBM3e, Chiplet, and CPO. From publicly verifiable information, JCET possesses a mature advanced packaging platform and continues to increase capital expenditures; however, the products, customers, and yields for "HBM3e mass production" require clearer disclosure.
JCET's potential advantages are its global customer system, large-scale OSAT manufacturing, and multi-platform combination capabilities. Whether it can achieve a breakthrough in HBM system packaging depends on whether it can secure long-term platform orders from top-tier AI chip customers, not just building production lines.
3.12 USI Electronics: HCoS Enters Customer Validation, a High-Potential but Immature 2.5D Platform
USI Electronics' HCoS-OR/OT and HCoS-AI/SI target 2.5D/3D high-computing power packaging. Exchange inquiry replies show that related products have already carried out agreement cooperation with multiple CPU, GPU, and communication chip customers, with samples entering reliability validation and customer introduction stages; documents also clarify that these products have no historical sales data and need to undergo mass production yield ramp-up.
Therefore, USI can be listed as a "potential participant in HBM system integration," but should not be equated with platforms that have stably mass-produced CoWoS or SmartPoser. The significance of its Phase III project lies in reserving space for future 2.5D/3D capacity; the real turning point is the translation of customer certification into continuous revenue.
3.13 Tiancheng Advanced and WY Semiconductor: Betting on TSV Platforms and Hybrid Bonding Respectively
Tiancheng Advanced's 12-inch wafer-level TSV 3D integration line has been put into production. The "Jiuzhong" platform covers 2.5D, 3D, and micro-assembly, and explicitly supports vertical stacking of memory chips and bare dies. WY Semiconductor, with Hybrid Bonding as its core, develops WoW, CoW, and 3D-IC platforms, and establishes technology platforms for memory chips. Both belong to important "capability providers" for the next generation of HBM interconnects, but public information does not prove that they have become mass production suppliers for HBM stacks.
From a technological trend perspective, as the number of stacking layers increases and interconnect pitch shrinks, hybrid bonding may gradually replace some micro-bumps; therefore, the strategic value of such platforms is very high, but commercial maturity must be judged by mass production line utilization rate, defect rate, customer products, and stable revenue.
3.14 Xinhengguang, Memory Technology, and Jingwang Shandong: Regional Memory Packaging Supplementary Nodes
Shandong Xinhengguang focuses on embedded memory chip packaging and testing, as well as SSD, USB flash drive, and module supporting; Shenzhen Memory Technology is listed in original articles as a memory SiP and testing enterprise; Jingwang Shandong provides CSP/WLCSP, bumping, RDL, and wafer testing. The scale and public information of such enterprises are relatively limited, making them more suitable to be classified as "regional mass production/supporting nodes." Their value lies in undertaking small-to-medium batches, embedded memory, and local customer demands, rather than directly participating in global HBM competition.
IV. Regional Map: Yangtze River Delta, Greater Bay Area, Central and Western Regions, and Bohai Rim
Figure 5 Regional Map of China's Memory Packaging (Drawn in this article)
Data Sources: Compiled from four regional packaging and testing industry competitiveness articles provided by users and public information.
4.1 Yangtze River Delta: The Most Complete Combination of "Scale OSAT—Memory Packaging/Testing—2.5D Platform"
The Yangtze River Delta simultaneously possesses multi-level entities such as JCET, TFME, Hua Tian, SJ Semiconductor, USI, Longsys/Yuancheng Suzhou, Taiji Industry, and CXMT. Its core advantage is not a single company, but the high-density synergy from conventional memory packaging and testing, high-end memory expansion, silicon interposers, RDL/bumping to third-party testing. Nanjing-Hefei-Nantong forms a high-end memory and HPC corridor, where Hefei jointly forms DRAM device and back-end synergy through CXMT, TFME, etc., while Shanghai Lingang-Jiangyin is closer to the AI/HBM system integration pole.
The challenges faced by the Yangtze River Delta are also the most direct: large-scale capital expenditures will form depreciation pressure. Only when customer certification, yield, and capacity utilization rate improve simultaneously can "project scale" be translated into "advanced packaging profits."
4.2 Greater Bay Area: Vertical Integration of Memory Product Companies into Packaging and Testing
The feature of the Greater Bay Area is not the scale of traditional OSATs, but terminals, modules, and memory product enterprises reversely building advanced packaging capabilities. Kaifa Technology/Payton provides the mass production base for DDR, LPDDR, UFS, and NAND; Biwin/Xingcheng Hanqi and Longsys/Yuancheng Suzhou combine product definition with packaging and testing; DMET forms an asset-light back-end synergy through in-house DIE/BGA testing and professional outsourced packaging; Tiancheng Advanced provides the TSV platform. This model can shorten the development cycle for edge AI memory, new modules, and customized products.
The shortcoming lies in the still insufficient experience with top-tier HBM customers and large-scale 2.5D mass production. A more realistic breakthrough for the Greater Bay Area is to first form differentiation in edge AI memory, SiP, ePOP, UFS, and fan-out memory, and then move up to HBM system integration.
4.3 Central and Western Regions: YMTC, SK hynix, and Hua Tian as Demand and Manufacturing Fulcrums
Wuhan YMTC provides full-chain 3D NAND demand, Chongqing SK hynix forms a DRAM back-end node, and Tianshui-Xi'an Hua Tian provides a comprehensive OSAT base. The advantage of the central and western regions is the existence of real memory IDMs and international manufacturing scenarios, which can form long-term orders and talent precipitation; its deficiency is the longer radius for advanced substrates, materials, equipment, and customer synergy, and the supply chain density between regional nodes is lower than that of the Yangtze River Delta.
4.4 Bohai Rim: Supplementary Chain Formation with Hybrid Bonding and Embedded Memory
The number of representative memory packaging entities in the Bohai Rim is relatively small, but their technical characteristics are distinct: WY Semiconductor bets on hybrid bonding and 3D-IC, Xinhengguang undertakes embedded memory packaging and testing, and Jingwang Shandong supplements WLP, RDL, and wafer testing. This region is more suitable for forming "technology platform + professional scenarios + project increments," rather than replicating the OSAT scale of the Yangtze River Delta in the short term.
V. Essence of Competition: Yield, Testing, Thermal Management, and Customer Binding
Figure 6 Business Model Differences of Four Types of Memory Packaging Enterprises (Drawn in this article)
5.1 First Barrier: KGD and Testing Data Closed Loop
Conventional memory packaging is already highly dependent on testing, and HBM further amplifies the importance of testing. If Known Good Dies cannot be identified before stacking, a single defective die can lead to the scrapping of the entire high-value stack; if system-level testing coverage is insufficient, problems will be difficult to locate among the GPU, HBM, interposer, and substrate. Therefore, testing equipment is just the foundation; the real barrier lies in test programs, failure mode databases, design for testability, and joint debugging with customers.
5.2 Second Barrier: Thermal and Mechanical Issues Determine Scalability
As the number of HBM layers develops from 8 and 12 to 16, dies become thinner, heat flux density is higher, and the warpage window is narrower. The fluidity of packaging materials, void filling, interface thermal resistance, packaging body coplanarity, and heat spreader design will jointly affect performance. This requires material suppliers, equipment manufacturers, OSATs, and system customers to collaboratively develop; relying solely on internal optimization by packaging and testing companies is difficult to accomplish.
5.3 Third Barrier: Customer Binding is More Important Than Nominal Capacity
Advanced packaging production lines are highly customized. Different GPU, HBM generations, and substrate solutions require different design rules, test programs, and reliability validation. Therefore, building a production line does not mean it can switch customers at any time. Truly valuable capacity is the capacity that has passed target customer certification, completed yield ramp-up, and formed stable scheduling. This is why leaders like TSMC and SK hynix can continuously obtain premiums, while new entrants, despite huge capital expenditures, still need a long introduction cycle.
5.4 Optimal Upgrading Path for Chinese Enterprises
● Step 1: Continue to strengthen the packaging and testing of DDR5, LPDDR5, UFS, eMMC, NAND, and SSD dies, training high-layer stacking, thinning, and testing capabilities with scale orders.
● Step 2: Develop FOMS, FC+WB hybrid packaging, 16D/32D high stacking, and wafer-level RDL/bumping to increase unit packaging value.
● Step 3: Form real customer delivery on 2.5D interposers, bridges, and high-density fan-out platforms, first cutting into the system integration of GPU + externally purchased HBM.
● Step 4: Establish joint development with domestic leading DRAM IDMs, AI chip companies, and material/equipment enterprises to achieve synergy in HBM stacks, logic base dies, and system packaging.
● Step 5: Use yield, testing coverage, thermal resistance, delivery cycle, and customer repurchase as evaluation indicators, rather than just announcing line width, layers, and investment amounts.
VI. Trend Judgment for 2026—2030
Figure 7 2026—2030 Memory Packaging Technology and Market Evolution Route
6.1 HBM4 Will Drive Further Integration of Packaging and Logic Manufacturing
HBM4 introduces more complex logic base dies and higher interface rates, requiring memory IDMs to coordinate earlier with foundries, GPU designers, and packaging platforms. Future HBM competition will no longer just be a battle of DRAM processes and stacking layers, but a joint optimization of logic base dies, interconnects, power supply, thermal management, and system architecture. This will enhance the influence of platforms like TSMC, Samsung Foundry, and Intel, and also create opportunities for OSATs with middle-end manufacturing capabilities.
6.2 Hybrid Bonding Will Gradually Enter High-Layer HBM, but Will Not Immediately Replace MR-MUF/TC-NCF
Hybrid bonding can shrink interconnect pitch, reduce parasitic parameters, and improve stacking height, making it an important candidate for 16-layer and higher HBM. However, it has extremely high requirements for surface flatness, particle control, alignment accuracy, and defect inspection, with obvious cost and yield pressure in the initial stage of mass production. Therefore, multi-route coexistence is more likely in the coming years: MR-MUF and TC-NCF will continue to serve mature mass production, while hybrid bonding will be gradually introduced in high-end products and specific layers.
6.3 Conventional Memory Packaging Will Be Repriced by AI, Not Eliminated by HBM
AI requires not only HBM but also server DDR5, enterprise SSDs, CXL memory expansion, mobile high-performance UFS, and edge AI memory. Therefore, the demand structure for conventional memory packaging will upgrade: higher frequencies, larger capacities, thinner packaging, higher stacking, and more complex testing. Enterprises with a conventional memory mass production base can still maintain stable cash flow and provide support for high-end packaging investments, as long as they continuously upgrade their product mix.
6.4 The Chinese Market Will See a Pattern of "Breakthroughs by a Few Platforms, Layering of More Enterprises"
In the next three to five years, there will not be a large number of enterprises in China simultaneously becoming HBM mass production suppliers. A more likely pattern is: a few companies enter top-tier customers in 2.5D system integration, TSV, or hybrid bonding; several memory OSATs continue to expand DDR/NAND back-end; memory product enterprises use advanced packaging for their own product differentiation; regional enterprises undertake embedded memory, modules, and small-to-medium batches. Industrial layering is not a failure, but an inevitable result of a mature supply chain.
VII. Conclusion
Memory packaging has formed two interdependent markets: a scale-oriented back-end market centered on DDR, LPDDR, NAND, UFS, eMMC, and SSD, and a high-end market centered on HBM stacks and GPU+HBM heterogeneous integration. The former determines whether an enterprise can form a stable manufacturing and testing system, while the latter determines whether an enterprise can enter the value highland of the AI computing power industry.
In the international competitive landscape, SK hynix, Samsung, and Micron control HBM stacks, while TSMC, ASE, Amkor, PTI, and Intel compete for system-level packaging. Chinese enterprises have already formed multi-level capabilities in conventional memory packaging and testing, including Kaifa Technology/Payton, Taiji Industry/Haitai, Hua Tian, TFME, Longsys/Yuancheng Suzhou, Biwin, DMET, Huicheng Electronics / Xinfeng Technology, YMTC, and CXMT, and are extending towards 2.5D/3D, TSV, and hybrid bonding through SJ Semiconductor, JCET, USI, Tiancheng Advanced, and WY Semiconductor.
In the future, those most likely to achieve the first breakthrough are not necessarily the enterprises that announce the largest investments, but those that simultaneously possess a conventional memory mass production base, real high-computing power customers, stable 2.5D yields, and advanced testing and material/equipment synergy. From the perspective of industrial pace, conventional memory packaging will still contribute to the base, and 2.5D HBM system integration will form a commercial breakthrough before the large-scale mass production of domestic HBM stacks.
References
[1] SEMI: Advanced Packaging: Driving Innovation, Performance and New System Capabilities, citing Yole's advanced packaging market forecast, 2025-12.
[2] SEMI: 300mm Fab Outlook / Public information related to 2026 memory equipment investment, 2026-06.
[3] SK hynix Newsroom: MR-MUF / Advanced MR-MUF technical description and HBM3E, HBM4, HBM4E product announcements.
[4] Samsung Semiconductor / Samsung Newsroom: HBM4 commercial shipment and HBM4E sample announcements, 2026.
[5] Micron: HBM4 high-volume mass production and 16-Hi 48GB sample related announcements, earnings call materials, 2026.
[6] TSMC: 3DFabric / CoWoS-S, CoWoS-L technical materials.