Changxin Memory Technologies (CXMT) is expected to launch a new generation of DDR5 RDIMM products by the end of this year, a message revealed by Cao Kanyu, President of CXMT, at the recently held 4th Integrated Circuits and Chiplets Conference. Cao Kanyu delivered a speech at the conference, comprehensively introducing the technological exploration and accumulation of CXMT in DRAM devices, the 4F² architecture, and hybrid bonding, and officially announced that the new generation of DDR5 RDIMM products expected to be launched by the end of the year integrates the aforementioned advanced technologies.
According to Cao Kanyu, CXMT initiated research and patent layout for the 4F² architecture since its establishment, with over 300 published patent families. CXMT published the first paper related to the 4F² architecture in mainland China in 2021, and shared R&D progress on this architecture in two papers in 2023 and 2025.
It is introduced that the most core feature of the CXMT 4F² architecture is the innovation in DRAM memory array transistors, namely the self-developed VSG (Vertical Surrounded Gate) transistor. The VSG transistor adopts a vertical surrounded gate structure, which can achieve stronger gate control, solve the pain points of leakage current and short-channel effects, and at the same time, the upright transistors also facilitate area scaling and improve storage density.
The short-channel effect is an inevitable problem for traditional horizontal structure transistors as the process scales down, leading to device threshold voltage drift and unstable performance; while the leakage issue has a more core impact on DRAM: the memory cells in DRAM rely on the amount of charge stored in the capacitor to distinguish between logic "1" and "0", and whether the capacitor can retain the charge directly determines whether the DRAM can work properly. If the leakage is too high, the charge in the capacitor will be lost quickly, and before the scheduled refresh time, the charge will be so low that it cannot be correctly recognized, directly causing data errors and even triggering system crashes. To mitigate leakage, the conventional industry practice is to increase the data refresh rate and frequently replenish the charge in the capacitor, but the refresh operation itself will consume extra power, crowd out the memory read/write bandwidth, slow down the response speed, and instead lower the overall performance-to-power ratio of the memory.
Currently, the mainstream architecture in the DRAM industry is the 6F² architecture. 6F² is a core metric for measuring the area of DRAM memory cells. In DRAM chip design, a memory cell usually consists of one transistor (1T) and one capacitor (1C). F (minimum feature size) represents the minimum line width or pitch that can be achieved by lithography technology in the wafer manufacturing process. 4F² means that each cell occupies only 4 times the square of the minimum feature size, so the number of transistors per unit area will increase, achieving an improvement in storage density.
The leap from 6F² to 4F² is essentially a fundamental transformation of the transistor channel direction from a horizontal layout to a vertical layout. This means that the design and process flow in the 6F² era cannot be completely reused, and a new set of process flows needs to be integrated. It is reported that during the R&D process, CXMT has carried out in-depth technological exploration and breakthroughs in multiple core process flows, comprehensively optimizing key processes including word line metallization, bit line formation, and junction activation, to achieve the optimal performance-to-power ratio.
In terms of integration methods, CXMT promotes the decoupling of DRAM and CMOS processes, and achieves high-speed interconnection through wafer-level hybrid bonding—this path is regarded as a key turning point for DRAM from 2D scaling to 3D integration. Early 4F² explorations focused on 2D transistor transformation, where the memory array and peripheral logic circuit manufacturing processes were bound together. Bit line transistors were forced to share the memory array process, resulting in slow response speed and high parasitic resistance. The performance was difficult to surpass the 6F² architecture, and related explorations were once shelved. As the scaling difficulty of 6F² increases, 4F² has once again become the industry direction. After the decoupling of DRAM and CMOS processes, logic performance, memory cell density, and reliability can be independently optimized. Since 2019, CXMT has promoted the independent R&D of hybrid bonding technology, and the number of published patents ranks among the top ten globally. In 2025, the company published a paper at IEDM, introducing the R&D results of the multi-layer horizontal cell stacked DRAM architecture, and completed the experimental verification of wafer-level bonding between DRAM and CMOS on a 12-inch wafer platform for the first time.
In terms of product commercialization, CXMT positions the first-generation product of the 4F² architecture as DDR5 RDIMM, directly facing the high threshold of server memory. DDR5 RDIMM is the mainstream configuration in the server market, requiring support for 7x24 hours of uninterrupted operation, withstanding hot-swap voltage shocks, completing hundreds of compatibility tests with CPUs and motherboards from different manufacturers and different generations, and ensuring that signals do not attenuate or produce errors on longer module traces during high-speed transmission. Consumer-grade memory pursues "running fast", while server-grade RDIMM pursues "running continuously, making no errors, and running anywhere".
CXMT believes that as technological accumulation is gradually transformed into products, it has the strength to compete with overseas peers in core architectures. The new architecture is expected to drive collaborative innovation in design, process, equipment, materials, and other links, promoting the transformation of the domestic storage industry chain.
Author | Zhang Xinyi
Editor | Wu Lilin
Art Editor | Ma Liya Supervisor | Lian Xiaodong