Recently, CXL (Compute Express Link) has become the focus of the storage and data center industries at the FMS 2026 conference. The core driving force lies in the demand for memory pooling and multi-tiered memory brought by AI large model inference. Vendors such as Montage Technology are accelerating the ecosystem layout of CXL 3.2 Memory Expander Controllers (MXC), marking the technology's formal transition from single-server memory expansion to system-level resource scheduling and multi-tiered memory architecture.
1. FMS 2026: CXL Memory Pooling Takes Center Stage, AI Inference Drives Architecture Evolution
CXL Addresses the "Stranded Memory" Pain Point in Data Centers
From August 4 to 6, the FMS 2026 conference was held in Santa Clara, California, USA. During the event, Samsung Electronics and SK Hynix conducted system validation focusing on CXL memory modules; interconnect chip vendors such as Marvell, Astera Labs, and Microchip continued to expand their controller, switch, and Retimer product lines. Kioxia attempted to introduce low-latency flash memory media like XL-FLASH into the CXL memory ecosystem.
As the AI infrastructure cycle advances, the boundary between memory and storage is gradually blurring. The challenges faced by data centers extend beyond the speed of writing data to SSDs (Solid State Drives); they also include determining whether the massive amounts of data generated by model parameters, long contexts, and high-concurrency inference should be placed in HBM (High Bandwidth Memory), local DDR, external memory, or SSDs.
AI training has driven the demand for GPUs and HBM, while scaled inference further amplifies issues with memory capacity and utilization. Model parameters and KV Cache (Key-Value Cache) continuously occupy memory; the higher the user concurrency and the longer the context, the greater the required capacity. Traditional server memory is constrained by CPU channels, DIMM slots, and overall system configurations, requiring the procurement of high-capacity DDR based on peak demand during purchasing. This leads to memory shortages in some nodes and long-term idleness in others, resulting in "stranded memory."
CXL offers a new solution: freeing a portion of memory from the server motherboard and expanding, tiering, and scheduling it through controllers and switch chips. For cloud service providers, its value lies in improving the utilization efficiency of existing DRAM and reducing long-term hardware investments reserved for peak loads.
CXL Industry Chain Ecosystem Approaches Deployable Status
The CXL product ecosystem is approaching a deployable status. CXL-supported CPU platforms, memory expander controllers, DRAM modules, switches, Retimers, and operating system support are gradually taking shape. This marks the first time, years after the introduction of CXL technology, that it has appeared at the center of the FMS stage with a relatively complete industry chain format.
Signals released at FMS 2026 indicate that the focus of CXL discussions has shifted from add-on memory for single servers to memory pooling, sharing, and tiering, with KV Cache in AI large model inference becoming the target scenario emphasized by vendors. Competition in AI infrastructure is extending from GPUs and HBM to host memory, data movement, and resource utilization.
Key CXL Vendor Developments at FMS 2026, Source: Compiled by eefocus Research Institute
2. Montage Technology Initiates Trial Production of CXL 3.2 Controller, MXC Market Enters Strategic Positioning Phase
Technical Specifications and Validation Progress of Montage Technology's CXL 3.2 Controller
On the eve of the FMS 2026 opening, Montage Technology announced the trial production of a new-generation CXL 3.2 memory expander controller, showcasing the chip and software development kits at the exhibition and CXL Mini DevCon. Designed based on PCIe 6.x and CXL 3.2 protocols, the product features a single-channel transmission rate of up to 64 GT/s, integrates dual DDR5 memory controllers, and supports up to DDR5-8000. It also integrates dual RISC-V processor subsystems, adapting to product form factors such as PCIe standard add-in cards (AIC) and EDSFF.
In CXL memory systems, the Memory Expander Controller (MXC) is a critical link connecting the server platform and DRAM modules. It must convert CXL memory access requests from the host into DDR commands and handle tasks such as address mapping, error management, monitoring, security, and firmware control.
Transitioning from CXL 2.0 to CXL 3.x, the product positioning has evolved from memory capacity expansion for single servers to further addressing memory pooling, sharing, and more complex Fabric architectures. The 64 GT/s rate corresponds to the high-speed links of the PCIe 6.0 era, while DDR5-8000 points to the next-generation server memory platform. Supporting AIC and EDSFF form factors means the controller must consider module design, server space, thermal management, power consumption, and mass deployment from the very beginning.
Samsung Electronics and SK Hynix have integrated Montage's CXL 3.2 controller into new-generation CXL module samples and completed the first round of system-level validation. The product is also being adapted for server platforms such as Intel Xeon and AMD EPYC, with target scenarios including KV Cache in AI large model inference and large-capacity memory demands. Such joint validations indicate that the controller has entered an ecosystem testing phase involving DRAM, CPU, and server vendors, shifting the competitive benchmark to "who can complete certification faster and enter customer systems."
Market Landscape of CXL Controllers, Switches, and Retimers
Montage Technology's entry into this market is related to its long-term accumulation of server memory interface capabilities. In the past, its advantages were concentrated in DDR memory interface chips such as RCDs (Register Clock Drivers) and DBs (Data Buffers). CXL controllers are more complex, but the customer base, memory technology accumulation, and platform validation experience are continuous. Compared to new entrants lacking a server customer base, Montage can more easily extend its existing relationships with DRAM manufacturers and the server ecosystem to CXL products.
Multiple players have emerged in the CXL field. Astera Labs entered the cloud computing and server customer base early with its Leo series, leveraging its commercialization experience with CXL 2.0 products and covering high-speed connectivity chips like Retimers. Marvell, through its Structera product line, combines CXL controllers with switch chips, DPUs, networking, and custom ASICs, betting on AI infrastructure and near-memory computing. Microchip, Rambus, and others have entered the market from the directions of storage controllers, PCIe/CXL interconnects, and IP licensing, respectively.
Montage and Astera Labs are closer to the general-purpose controller market, with competition focusing on CPU adaptation, DRAM compatibility, module reference design, and customer validation. Marvell attempts to integrate CXL into a broader AI infrastructure product portfolio to enhance customer stickiness through system value. IP vendors like Rambus lower the threshold for other chip companies to enter the CXL market through licensing. As protocols and hardware become standardized, MXCs may develop into a relatively independent chip category; whether they can enter the mainstream server supply chain depends on long-term interoperability and mass production validation.
If the MXC solves "how to connect memory to the server," the CXL Switch solves "how to organize distributed memory into resource pools." This is the most incremental segment in the next phase of the CXL industry. Marvell, Broadcom, Microchip, XConn, and others are all deploying in the switch chip market. Switches need to connect multiple hosts and multiple CXL devices, undertaking resource partitioning, path management, QoS, fault isolation, and Fabric management. Their port scale, latency, and management capabilities directly determine the expansion scope of the memory pool.
Retimers represent another incremental market. CXL 3.x is built on 64 GT/s high-speed links; as the rate increases, signal attenuation on server motherboards, connectors, and cables becomes more pronounced. Complex topologies typically require Retimers to recover signals and extend transmission distances. Vendors with PCIe high-speed interconnect capabilities, such as Astera Labs, Microchip, Broadcom, and Montage Technology, all have the opportunity to capture demand in this segment. Compared to MXCs, Retimers have stronger universality, serving GPUs, network cards, SSDs, and other PCIe devices, making it easier to achieve economies of scale.
Memory Manufacturers Shift to Third-Party MXC Solutions Amid Software Ecosystem Challenges
Memory manufacturers such as Samsung, SK Hynix, and Micron have scaled back or adjusted their in-house CXL commercialization routes to varying degrees in recent years, shifting towards adopting third-party controller solutions (MXCs). Adopting third-party solutions validated across multiple platforms can shorten the time-to-market for CXL memory modules. This division of labor benefits the expansion of the CXL ecosystem but also increases the complexity of cross-vendor compatibility and system validation.
Module and supporting chip vendors will gain new opportunities. A CXL memory module, in addition to DRAM and MXC, requires components such as PMICs (Power Management ICs), SPDs (Serial Presence Detect), or VPDs (Vital Product Data). Professional storage module vendors like Longsys can leverage their manufacturing, testing, and customer channels to integrate controllers and DRAM into standard products.
The most difficult to quantify yet potentially value-determining link in the supply chain is software. CXL hardware provides additional capacity, while software determines which data remains in local DDR, which migrates to CXL memory, and how different servers request and release resources. Without mature tiering algorithms and resource management, the added remote memory may introduce higher latency without improving overall utilization. Currently, Linux, virtualization platforms, and upper-layer applications still need to continue adapting to CXL.
Comparison of Global Major CXL Chip Vendors and Product Layouts, Source: Compiled by eefocus Research Institute
3. CXL Technology Trends: From Memory Expansion to Multi-Tiered Memory and Software Definition
Expansion of CXL Connection Media and Formation of Multi-Tiered Memory Architecture
Information released at FMS 2026 shows that CXL will next advance simultaneously in three directions: memory expansion, resource pooling, and multi-tiered memory. Over the next two to three years, the CXL market may form two parallel routes: one is a relatively mature expansion market, primarily carried by CXL memory cards and modules; the other is a pooling market still under validation, led by switches, Fabric management, and cloud service providers.
The media connected by CXL will no longer be limited to DRAM. Vendors like Kioxia are beginning to attempt connecting low-latency flash memory such as XL-FLASH to CXL, aiming to fill the performance and cost gap between DRAM and NVMe SSDs. Future servers may form a multi-tiered system consisting of HBM, local DDR, CXL DRAM, SCM (Storage Class Memory), and NVMe SSDs.
In this architecture, the hottest data remains in HBM or local DDR; data with large capacity demands but lower access frequencies is placed in CXL DRAM; and further cooled data enters SCM, low-latency Flash, or SSDs. For memory manufacturers, the competitive focus is no longer just on providing larger-capacity DRAM or NAND, but also on how to integrate different media into a unified data tier. For controller vendors, product capabilities will expand from protocol conversion to media management, performance monitoring, and quality of service control.
Core of CXL Commercialization: Software Scheduling and Long-Term TCO Advantages
Whether multi-tiered memory can achieve its expected value ultimately depends on software. Hardware can only provide storage tiers with different speeds and costs; the operating system and applications need to determine which tier data should be placed in and migrate it after access patterns change. Inaccurate identification of hot and cold data can lead to frequent page migrations consuming bandwidth; if core data is placed in higher-latency CXL memory, system performance may instead decline. Data shows that CXL still incurs additional access overhead compared to local DDR, and operating systems, virtualization platforms, and upper-layer applications need to continue improving memory tiering and scheduling capabilities.
The CXL value chain may gradually shift from hardware to software. In the early market, focus was on controller speeds, memory channels, and module capacity; upon entering the pooling and multi-tiered memory stages, customers pay more attention to page migration algorithms, resource pool orchestration, QoS, fault management, and optimization for specific workloads such as AI inference and databases. Vendors capable of simultaneously providing controllers, SDKs, management tools, and application adaptation solutions are more likely to build customer stickiness than those merely selling chips or memory cards.
Another critical variable for commercialization is return on investment. Deploying CXL systems increases costs for controllers, switches, Retimers, modules, and software development, and may also bring additional power consumption. Data center procurement decisions are based on how much high-capacity DDR configuration CXL can reduce, how much idle memory it can revitalize, how many servers it can decrease, and whether it can improve GPU and CPU utilization. Data reminds that the long-term TCO (Total Cost of Ownership) advantage of CXL relies on software scheduling and resource management; if the system cannot achieve a sufficiently high resource utilization rate, the new hardware investment will be hard to recoup.
The future technical direction of CXL is clear: moving from single-machine expansion to pooling, from single DRAM to multiple media, and from hardware connection to software definition. However, commercialization will not happen synchronously. Memory expansion has entered the customer validation and early deployment stage; pooling and sharing still need to complete system-level validation; and multi-tiered memory must wait for the software ecosystem to mature. The true turning point for CXL is when data centers can use actual operational data to prove that the increased system complexity can be exchanged for lower memory costs, higher resource utilization, and more flexible computing power deployment.
4. CXL Reshapes Storage Market Landscape, Forming Differentiated Division of Labor with NVLink
CXL Does Not Replace HBM and NVMe, Reshaping Memory Value Distribution
CXL is not a storage technology that replaces DDR, HBM, or NVMe. CXL itself is a set of interconnect and memory access protocols; it does not produce data storage media, nor does it eliminate performance differences between different media. The change it brings is the redivision of the positions of memory and storage technologies in servers: determining which data must be placed in the most expensive and fastest memory, which data can be migrated to tiers with larger capacity and lower costs, and which resources can be freed from the fixed configuration of a single server.
CXL memory devices currently still heavily adopt DDR4 or DDR5 chips, and their development will not weaken the overall demand for DRAM capacity in data centers. CXL changes the value distribution of high-capacity server memory. In the future, customers may purchase not only more DDR chips but also MXC controllers, module designs, memory pool management, and tiering software. Memory manufacturers still hold the advantage in media manufacturing, but controller vendors, switch vendors, and software companies will enter the server memory value chain, which was previously dominated mainly by CPU and DRAM manufacturers.
CXL cannot replace HBM, but it may reduce the pressure on some applications to solve problems by infinitely increasing HBM capacity, driving AI systems to shift from merely stacking high-bandwidth memory to more refined data tiering. CXL will also not directly replace NVMe. CXL is suitable for carrying data that requires near-memory access methods but has a capacity larger than local DDR; NVMe is responsible for larger-scale, lower-cost data that requires persistent storage. Future data centers may add one or more CXL tiers between DRAM and NVMe, transforming the originally simple "memory plus SSD" architecture into a multi-tiered system including local DDR, CXL DRAM, SCM, low-latency Flash, and NVMe SSDs.
SSD Market Impacted, Strategic Position of SATA/SAS Declines
For SSD vendors, this change brings both pressure and new markets. Some high-speed caches or temporary data that previously relied on NVMe SSDs may be diverted by CXL DRAM and storage-class memory; low-latency Flash, CXL SSDs, and new types of persistent memory may also enter tiers closer to the CPU. Kioxia's display of CXL memory expansion modules based on XL-FLASH at FMS 2026 is precisely seeking a new performance and cost range between DRAM and NVMe SSDs.
As CXL further improves server memory and data access efficiency, high-performance data centers will focus more on PCIe, NVMe, and memory-semantic interconnects. SATA (Serial ATA) and SAS (Serial Attached SCSI) may continue to retreat to cold data, archiving, traditional disk arrays, and some enterprise markets requiring long-term compatibility. They will not disappear in the short term, but their strategic position in AI servers and newly built high-performance data centers will continue to decline.
Long-Term Competitive Mainline Between CXL and NVLink Proprietary Interconnects
CXL will also face long-term competition from proprietary interconnect technologies such as NVLink. NVLink and NVSwitch focus on high-speed communication between GPUs and have formed a mature closed ecosystem in NVIDIA AI systems. The advantage of CXL lies in its openness and universality, capable of connecting CPUs, accelerators, memory, and devices from different vendors, but it is temporarily difficult to surpass proprietary interconnects in extreme bandwidth and latency. NVLink's performance advantage in large GPU clusters will limit CXL's application space in intra-GPU interconnect scenarios.
A division of labor is more likely to form in the future: NVLink serves high-bandwidth GPU interconnects within the same AI platform, while CXL is responsible for open connections between CPUs, accelerators, memory expansion devices, and broader data center resources. Whether open standards can gain more platform support and whether proprietary protocols can maintain performance leadership will become the long-term competitive mainline in the AI interconnect market.
CXL controllers are becoming new entry points between different computing platforms, memory media, and server systems. It will not disrupt the traditional storage market in the short term, but it will change the distribution of industrial value. In the past, the market focused on who could produce faster memory and larger-capacity SSDs; in the future, competition will extend to who can connect these media, manage data tiers, and allocate memory resources to the computing tasks that need them most at a lower cost.
5. Frequently Asked Questions (FAQ) on CXL Technology
What are the main application scenarios for CXL memory pooling technology in 2026?
The core scenarios are KV Cache storage and large-capacity memory demands in AI large model inference. By freeing a portion of memory from the server motherboard via CXL for expansion, tiering, and scheduling, it solves the memory capacity and utilization bottlenecks caused by high-concurrency inference and reduces hardware investments reserved for peak loads.
What is the current competitive landscape of the CXL controller (MXC) market?
Montage Technology and Astera Labs focus on the general-purpose controller market, competing in CPU adaptation and DRAM compatibility; Marvell combines CXL with DPUs and networking to bet on AI infrastructure; Rambus and others lower the threshold through IP licensing. Memory manufacturers such as Samsung and SK Hynix have shifted to adopting third-party MXC solutions to shorten time-to-market.
Will CXL replace HBM or NVMe SSDs?
No. CXL is a set of interconnect and memory access protocols and does not produce storage media. It cannot replace the high bandwidth of HBM, but it can alleviate the pressure of infinitely increasing HBM capacity; it will also not replace the large-scale persistent storage function of NVMe SSDs, but rather adds new data tiers between DRAM and NVMe, promoting the formation of a multi-tiered memory architecture.