On September 20, ChangXin Memory Technologies (CXMT) announced the mass production of its 5th-generation DRAM technology platform (G5) at the 2026 World Manufacturing Convention, simultaneously showcasing two 24Gb LPDDR5X products based on this platform. The four key figures provided by the company are: an active area half-pitch of 11.95nm, a capacitor aspect ratio of 45:1, a core functional area height of 6762nm, and at least a 50% increase in die per wafer (DPW) compared to the previous generation.
In the context of the DRAM narrative, the significance of this milestone lies not in the term "5th generation," but in the path to achieving it—pushing the process to the scale of the industry's 1c node without EUV (Extreme Ultraviolet) lithography. However, it is equally important to clarify: generational alignment does not equal cost alignment, and each of these four figures has its own specific context.
PART 01: The Reference Frame of 11.95nm
First, let's clarify a point that is often vaguely handled. The 11.95nm refers to the "memory array active area half-pitch," which measures a specific structure in the array region. In contrast, Samsung, SK Hynix, and Micron use node naming conventions like "12nm class" or "11nm class" for external communication. The two are not on the same scale and cannot be directly equated—a point already highlighted in reports by foreign media such as the Seoul Economic Daily.
However, even under the most conservative comparison, 11.95nm indeed falls at the upper edge of the industry's most advanced mass production range. SK Hynix's 1b node has an actual design dimension of approximately 12–13nm, equipped with 4 EUV layers; the 1c node shrinks to about 11–12nm, equipped with 5–6 EUV layers. CXMT's figure roughly aligns with the 1c side.
The key point to note is the method of achievement. Affected by export controls, EUV lithography equipment has yet to enter the mainland market. CXMT has adopted DUV (Deep Ultraviolet) multi-patterning—splitting a single layer pattern into four overlapping exposures, trading process steps for resolution. The costs are clear: an increase in mask layers, higher overlay accuracy requirements, increased difficulty in defect density control, and longer unit process times. The industry has long questioned the economic viability of "pushing advanced nodes with DUV," and G5 is precisely answering this question.
Accompanying the quadruple patterning is a set of modules migrated from logic processes. HKMG (High-k Metal Gate), which previously primarily served advanced logic, has been adapted into the DRAM process this time to reduce the height of the core functional area. Additionally, there are saddle-fin structures, low-k spacer bitlines, and interface engineering. The simultaneous implementation of these processes indicates that G5 is not a single-point breakthrough, but an overall downward shift of the process stack. The digital twin system introduced on the R&D side covers the entire process of design, development, manufacturing, and maintenance, and its value lies here as well—it solves not "whether it can be made," but "whether it can be stably and repeatedly manufactured." For a manufacturer advancing along a generational sequence, the difficulty of the latter is no less than that of the former.
PART 02: The Context of the 50% Figure
The most easily misinterpreted figure in the official statement is the "+50%."
Its full statement is "the number of die per wafer (DPW) increases by at least 50% compared to the 4th-generation platform (all converted to an 8Gb die baseline for statistics)." Two limitations must be clearly understood: first, this is the theoretical count before defect screening, which is a different concept from the yield that determines actual shipments; second, CXMT has not disclosed the yield level and monthly output of G5. The official display board itself also notes that "there are normal fluctuation deviations in the mass production of actual products."
The capital-intensive logic determines the weight of this matter. The investment in a 12-inch DRAM fab is in the tens of billions of USD range. The number of usable chips cut from each wafer directly determines the unit cost. A 50% increase in DPW theoretically corresponds to a significant reduction in unit manufacturing costs. However, between "design density" and "sellable capacity" lies the yield ramp-up curve—it will not be realized instantly, nor will it instantly impact global prices.
On the cost side, another set of figures is worth noting: industry estimates suggest that CXMT's current cost per bit is still higher than that of the three major giants. The specific numerical estimates may not be entirely precise, but the fact they point to is clear—the process generation has aligned, but the cost structure has not. "Process capabilities on par with the industry's top mass production nodes" refers to the former, not the latter. This is the true commercial test for G5: it needs to prove not just "it can be made," but "it can be made cheaply." The former is technical validation; the latter is what mass production truly means.
PART 03: Complementary Positioning Rather Than Direct Substitution
Shifting the focus from process to business, CXMT's current position is more nuanced than that of a "chaser."
The capacity of the three major giants is systematically shifting towards HBM (High Bandwidth Memory) and server DDR5, creating structural vacancies in general product lines (DDR4, standard DDR5, and low-to-medium capacity LPDDR). CXMT is exactly capturing this segment. According to TrendForce data, its global DRAM revenue share in the second quarter of 2026 was approximately 9.5%, ranking fourth. This figure is not exceptionally high, but it is the only player outside the top three that is scaling up, and it is still climbing.
The shift on the client side illustrates this even more clearly. The Nubia NaviX Ultra is equipped with CXMT's 10667Mbps LPDDR5X, marking the first large-scale commercial use of domestic chips in this speed range; the Xiaomi 18 Fold features the debut of CXMT's LPDDR6, with a peak speed of 12800Mbps. The semi-annual report disclosed that LPDDR5/5X has entered the supply chains of Xiaomi and Transsion, and automotive-grade LPDDR5X is also in mass production. Flagship smartphones are simultaneously sensitive to memory speed, power consumption, package size, and cost; failure to meet any standard will result in being replaced. Being able to enter both of these clients indicates that the performance threshold has been crossed, not the emotional one.
The timing of LPDDR6 deserves special mention: CXMT announced mass production on August 29, making it the world's first to land LPDDR6; SK Hynix and Samsung plan to ship in the second half of 2026, while Micron expects full commercialization in 2027. This is the first time domestic DRAM has achieved "no lag in first launch" in terms of product generation, and the G5 platform serves as the process foundation for its subsequent supply.
The shortcomings are equally clear. The protagonist of G5 is mobile LPDDR, while server DDR5 and HBM have not yet taken the lead. CXMT's gap with the three giants in HBM is far greater than its gap in general DRAM; its HBM3E is currently only in the state of "reportedly entering trial production," without official confirmation. The highest-value increment in AI (Artificial Intelligence) computing power (HBM) remains out of CXMT's reach, which determines that at this stage, it is more like a "complementary player in general storage" rather than a "challenger in high-end computing power."
PART 04: Divergence in Supply and Demand Judgments
Regarding the judgment of the cycle, the market itself is divided.
On the bullish side, Citigroup estimates that global DRAM demand will grow by 30% and supply by 19% in 2027; in 2028, demand will grow by 35% and supply by 22%, with the shortfall driven by AI training-induced HBM and server DDR5. On the bearish side, Acer Chairman JT Chen stated on September 19 that with the release of mainland capacity, PC memory is no longer in short supply, and for some part numbers of DDR4, LPDDR5, and DDR5-9600, sellers even outnumber buyers. He expects the momentum of price increases may halt in the second half of next year.
The two judgments are not necessarily contradictory: the shortage is concentrated in HBM and high-speed server DDR5, while the supply and demand for general part numbers are already loosening, and the release of CXMT's capacity is precisely one of the important sources of this loosening. This also means that the scale of the memory cycle is always hanging over CXMT's growth logic—whether technical dividends can be translated into profits depends on the timing and magnitude of price retracements. DRAM is a highly cyclical business; in a downcycle, only those with the lowest costs can survive.
PART 05: What to Observe
Capital and technology are synchronized in this round. On July 27, CXMT Technology listed on the SSE STAR Market. With an issue price of CNY 8.66 and a fundraising scale of CNY 57.9 billion, it became the largest IPO in the history of the SSE STAR Market; the total market capitalization at the close of the first day was approximately CNY 3.28 trillion, topping the A-share market, and later briefly exceeded CNY 4 trillion. In the first half of 2026, revenue reached CNY 150.31 billion, a year-on-year increase of 873.64%, and net profit attributable to the parent company was CNY 77.605 billion, wiping out all accumulated losses since its establishment in one go. Launching G5 at this point is a synchronization of performance realization and technological narrative.
Returning to G5 itself, what is worth tracking is not the sequence number "5th generation," but three things: the actual slope of the yield ramp-up, the speed at which the cost per bit converges towards the three giants, and when HBM will transform from rumors into products. The first two determine whether this path of "bypassing EUV" can be sustained, and the third determines whether CXMT can transition from a complementary player in the general market to a participant in the computing power era.
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