Abstract: During the recently concluded WAIC 2026, domestic AI computing chip companies showcased general-purpose GPUs, NPUs, TPUs, 3D near-memory computing, edge inference chips, and super node systems. Manufacturers such as Huawei, Alibaba Cloud, Moore Threads, MetaX, Biren Technology, and Enflame Technology have shifted their competitive focus from single-chip parameters to Scale-up high-speed interconnects, unified memory, software stacks, model adaptation, and large-scale delivery. Meanwhile, companies like Iluvatar CoreX, Zhonghao Xinying， and Dongfang Suanxin are seeking differentiated paths through general-purpose GPUs, specialized AI computing, and near-memory computing, respectively.
The 2026 World Artificial Intelligence Conference (WAIC) was held in Shanghai from July 17 to 20. Themed "Intelligent Partners Co-creating the Future," computing chips remained one of the most watched technology sectors in the exhibition halls. However, the most eye-catching products on the booths have shifted from single accelerator cards to cabinets, super nodes, and large-scale computing systems. Companies including Huawei, Alibaba Cloud, Moore Threads, MetaX, Biren Technology, and Enflame Technology intensively showcased super node products, while Iluvatar CoreX, Zhonghao Xinying, and Dongfang Suanxin advanced new chip and system solutions in the directions of general-purpose GPUs, TPUs, and 3D near-memory computing, respectively.
Over the past few years, the primary questions domestic AI chip companies had to answer were whether the chips could be powered on, whether they could run mainstream frameworks, and whether they could complete large model training or inference. As products gradually enter data centers, customer inquiries have become more specific: Can hundreds of cards collaborate stably? How long does model migration take? Can tasks continue after a single-card failure? What are the Token throughput, energy consumption, and O&M costs of the entire system?
This means that domestic computing competition is moving beyond the single-chip stage. While chips remain the underlying foundation, the actual capability of an AI computing system increasingly depends on the systemic efficiency formed jointly by chips, memory, interconnects, servers, liquid cooling, communication libraries, compilers, and model adaptation.
The signals released from this WAIC 2026 can be roughly summarized as follows: domestic AI computing power is shifting from "competing on single-card parameters" to "competing on system capabilities and large-scale delivery."
Why Have Super Nodes Suddenly Become the Protagonists?
What is a super node? Source: Drawn by eefocus Research Institute
A super node is not merely packing many GPUs into the same server room, nor is it just increasing the number of servers. It aims to organize dozens, hundreds, or even thousands of AI chips into a larger computing unit through high-bandwidth, low-latency Scale-up interconnects.
To understand super nodes, one must first understand how large models utilize chips.
When the model scale is small, a single GPU or server can accommodate all model parameters. As models grow larger, parameters, activation data, and KV Cache cannot all fit into the VRAM of a single chip, forcing the system to split the model across multiple chips. Different chips take charge of different layers, parameters, or computing tasks within the model, continuously exchanging intermediate results.
MoE models further elevate communication demands. An MoE model contains numerous "experts" internally, activating only a subset of them for each computation. These experts may be distributed across different chips or even different servers, requiring Tokens to be frequently routed between chips. Long contexts, multimodal data, and high-concurrency inference also increase VRAM and interconnect pressure.
At this point, chip computing speed is only part of the system performance. If data transmission between chips is too slow, a massive number of computing units will halt and wait. Although peak computing power is high, the effective computing power actually used for model operations may be far below the theoretical value.
Traditional AI clusters primarily rely on Scale-out expansion. Multiple servers are connected via Ethernet, InfiniBand, or other networks, and the overall scale is expanded by adding more servers. This architecture offers flexible deployment, but cross-server communication usually has to pass through NICs, switches, and multiple software layers, making it difficult for latency and bandwidth to reach the level of intra-server interconnects.
Super nodes, on the other hand, attempt to expand the Scale-up high-speed computing domain. Within this computing domain, more AI chips are tightly connected via dedicated interconnect protocols, and some systems even provide unified memory addressing or a unified resource view. For upper-layer software, these chips resemble a single large computer rather than a multitude of independent servers.
A standard AI cluster can be compared to many scattered small teams. Each team has its own personnel and materials, and cross-team collaboration requires repeatedly passing files. A super node is more like a large team with highly tight internal collaboration, where all members share unified task scheduling and material directories, resulting in shorter communication paths.
Huawei's definition of a super node is relatively direct: physically composed of multiple machines, but logically learning, thinking, and reasoning like a single computer. Its Atlas 950 SuperPod uses a 64-card cabinet as the basic unit, builds a large-scale Scale-up computing domain through the Lingqu interconnect, and adopts unified memory addressing to reduce the complexity of multi-chip resource management. The product was released in March 2026 and made its public debut as a physical machine during WAIC.
However, the number of cards in a super node cannot be directly equated with model performance. To judge whether a super node solution is mature, at least five indicators must be observed:
First is interconnect bandwidth and communication latency. Bandwidth determines how much data can be transmitted per unit of time, while latency determines how long a chip must wait after issuing a request.
Second is the effective utilization rate of the cluster. The more time chips spend genuinely participating in computation, the higher the proportion of peak computing power converted into effective computing power.
Third is model throughput, including the volume of data processed per unit of time during training and the number of Tokens generated per second during inference.
Fourth is reliability. With hundreds or even thousands of cards running for extended periods, failures in single cards, links, and switching equipment are highly probable. The system must be able to isolate faults, reorganize the topology, and resume tasks from breakpoints.
Fifth is the Total Cost of Ownership (TCO). Super nodes require supporting power supply, liquid cooling, networking, and server room space, and an increase in the number of cards also raises O&M complexity. What customers ultimately purchase is not a set of attractive peak parameters, but a production system capable of stably outputting Tokens over the long term.
From Huawei to Alibaba Cloud, Super Nodes Begin to Form Diverse Technical Routes
Summary of Partial Computing Chips, Source: Drawn by eefocus Research Institute
The Atlas 950 SuperPod exhibited by Huawei at the WAIC site represents one of the largest-scale system routes among current domestic super nodes. According to public information, the product uses a 64-card cabinet as the basic unit, supports high-speed interconnection of up to 8,192 NPU cards, and adopts the Lingqu protocol, UB-Mesh recursive direct-connect topology, and unified memory addressing, targeting ultra-large-scale training and high-concurrency inference. Huawei also simultaneously showcased CANN, the Mind series of foundational software, and multiple industry application cases, emphasizing the synergy of hardware, foundational software, and industry ecosystems.
Here, it is necessary to distinguish between two concepts: super nodes and super node clusters. Inside a super node, Scale-up interconnects are primarily used to form a high-speed computing domain with more chips; multiple super nodes can also be further organized into larger clusters via Scale-out networks. Huawei's previously disclosed Atlas 950 SuperCluster continues to expand using multiple Atlas 950 super nodes as basic units. Super nodes solve local efficient collaboration, while clusters solve overall scale expansion; together, they constitute the infrastructure for large model data centers.
Alibaba Cloud's Panjiu AL128 adopts a product form of 128 chips per single cabinet. Its core computing chip, Zhenwu M890, uses T-Head's self-developed parallel computing architecture, configured with 144GB of VRAM and 800GB/s chip-to-chip interconnect bandwidth, supporting multiple precisions from FP32 to FP4. The Panjiu AL128 organizes 128 AI chips into a single computing node through ALink interconnects and self-developed switching chips. This product has been integrated into Alibaba Cloud Bailian, supporting models such as Qwen, DeepSeek, and Kimi.
The Zhenwu M890 and Panjiu AL128 were released at the Alibaba Cloud Summit in May 2026; this WAIC primarily serves the role of centralized display and ecosystem promotion, and should not be written as the conference premiere. More notably, Alibaba Cloud is beginning to place chips, super nodes, cloud platforms, model services, and software stacks within the same product system. According to a report by Yicai, T-Head's open-source SAIL software architecture covers the operating system, SDK, and interface layers, and is adapted to multiple mainstream training and inference frameworks. For cloud service providers, the value of self-developed chips lies not only in substituting external GPUs but also in deeply integrating hardware with model platforms, scheduling systems, and cloud services.
Moore Threads publicly debuted the MTT C256 super node at WAIC. Public data shows that the system achieves full interconnection of 128 cards within a standard single-width cabinet, and two cabinets can form a one-layer Scale-up network of 256 cards. Compared with multi-layer switching networks, one-layer interconnects can reduce intermediate switching layers, lowering communication paths and latency, but also imposes higher requirements on switching chips, wiring, and system topology.
Moore Threads' display highlights also included the "Model Training Factory, Token Production Factory, and Agent Production Factory." The company disclosed that its system has completed zero-to-one training for some MoE models, launched a PD disaggregation inference solution based on the MTT S5000, and adapted to models such as DeepSeek and MiniMax. The concept of "factory" here reflects that the product logic of computing power companies is changing: what customers need is a continuous production environment for model training, inference, and agent development, with the GPU being just one part of it.
MetaX premiered the Xijing S-series super node and the Xisuo X300-series scientific AI GPU at WAIC. The Xijing S600 adopts a single-cabinet 64-card design, supporting multi-dimensional parallelism such as EP and TP, targeting large model training and inference; the Xisuo X300 targets AI4S scenarios such as meteorology and oceanography, fluid mechanics, molecular dynamics, materials, and life sciences.
These two product lines reflect the gradually diverging trend of training, inference, and scientific computing. Large model training values mixed-precision computing, multi-card interconnects, and long-term stability; inference emphasizes concurrency, latency, VRAM utilization, and Token costs; traditional scientific computing requires relatively complete floating-point precision, scientific computing software, and a high-performance computing ecosystem. It is increasingly difficult to cover all workloads with a single chip and a single set of software.
Interconnects Are Becoming a Competitive Focus as Important as Chip Architecture
As the scale of super nodes expands from 8 cards and 16 cards to 64 cards, 128 cards, and beyond, the system bottleneck will gradually shift from computing units to interconnects.
Biren Technology launched a super node solution based on the BR2xx GPU, BLink 2.0 interconnect protocol, and NPO optical interconnect at WAIC, forming a product roadmap of 16-card servers, 128-card full cabinets, and up to 1,024 cards. The BR2xx continues the Chiplet architecture and supports FP8 and FP4, while BLink 2.0 emphasizes memory semantic interconnects, in-network computing, congestion control, and link self-healing.
The goal of memory semantic interconnects is to enable different chips to exchange data in a manner closer to accessing local memory, reducing explicit copying and communication management at the software level. In-network computing offloads some communication operations, such as reduction and aggregation, to switching equipment, avoiding the need for all data to return to the GPU for processing. These technologies will not make communication costs disappear, but they have the opportunity to reduce the occupation of computing units by data movement.
The 1,024-card solution proposed by Biren Technology still belongs to the product roadmap and system planning and cannot be directly equated with customer deployments of the same scale already in place. For super nodes to move from design to commercial delivery, they must still undergo verification of servers, optical modules, liquid cooling, firmware, software, and long-term stability.
Enflame Technology showcased the Yunsui ESL64-O, ESL64-C, and NPO optical interconnect prototypes at WAIC. The ESL64-O adopts an orthogonal architecture, while the ESL64-C uses a Cable-tray wiring scheme; the two represent different engineering implementations of internal connections within super nodes. The orthogonal backplane-less design allows computing boards and switching boards to connect directly, shortening signal paths and reducing some cabling; the Cable-tray scheme is relatively mature, with deployment and maintenance paths closer to existing data centers.
As connection distances and transmission rates increase, copper interconnects face pressure from signal attenuation, power consumption, and wiring density. NPO, or Near-Package Optics, attempts to place the optical engine close to the switching chip or computing chip to shorten the transmission distance of high-speed electrical signals, and then uses optical fibers to complete longer-distance connections. Both Biren and Enflame showcased the NPO route simultaneously, indicating that optical interconnects are moving closer from inter-cabinet networks in data centers to the inside of super nodes.
Optical interconnects are not simply a replacement for copper cables. Optical module costs, packaging yield, heat dissipation, maintenance methods, and optoelectronic conversion power consumption will all affect the final solution. In the near future, data centers are more likely to form hierarchical interconnects: electrical interconnects will remain the mainstay inside chips and for short distances, while the proportion of optical interconnects will gradually increase for inter-cabinet connections and larger-scale super nodes.
General-Purpose GPUs Continue to Evolve, and Product Evaluation Begins to Shift to Token Efficiency
Iluvatar CoreX officially released the new-generation general-purpose GPU Tiangai 300 at WAIC. Based on the SIMT general-purpose computing architecture, the chip is optimized around Attention, MoE, AF disaggregation, PD disaggregation, and large-scale system expansion. The company also stated that the Tiangai 300 is being adapted with cloud vendors, server vendors, and super node systems.
The SIMT architecture enables a massive number of threads to execute the same or similar instructions, making it suitable for matrix operations and highly parallel AI workloads. The advantage of general-purpose GPUs lies in their broad applicability, covering training, inference, scientific computing, and some graphics computing; the trade-off is higher complexity in chips and software systems, requiring substantial resources to build compilers, runtimes, communication libraries, and development tools.
Iluvatar CoreX published internal test comparisons with Hopper architecture products, but these data come from the company's test environment. Model configurations, precision, parallel strategies, and system conditions may affect the results, making them more suitable as a reference for product optimization directions. The industry still needs independent testing and unified benchmarks to judge the true efficiency of different domestic GPUs.
Low-precision computing is a common direction for multiple products at this WAIC. Both the Zhenwu M890 and Biren BR2xx explicitly support FP4, and Huawei also announced FP4 computing power at the super node level. FP4 and FP8 can reduce the space occupied by model weights and activation data, lower VRAM and data transmission pressure, and improve inference throughput under the premise of acceptable model precision.
However, TOPS and TFLOPS at different precisions cannot be directly ranked together. One product might announce FP4 sparse computing power, while another announces BF16 dense computing power, and edge chips often use the INT8 metric. Even if the numbers are the same, the actually runnable models, power consumption, and precision may be completely different.
Entering the inference era, more reference-worthy metrics are becoming Time to First Token (TTFT), Decode speed, number of concurrent requests, energy consumption per Token, and cost per million Tokens. What computing chips ultimately need to solve is Token production efficiency, rather than just creating larger peak numbers on parameter sheets.
PD disaggregation is a system optimization targeting inference workloads. Large model inference is usually divided into two stages: Prefill and Decode. Prefill needs to process user input and is highly compute-intensive; Decode generates answers Token by Token, relying more on VRAM bandwidth and communication. Deploying the two stages on different hardware or resource pools can reduce mutual interference and improve overall resource utilization. Both Moore Threads and Iluvatar CoreX emphasized PD disaggregation in their WAIC-related products, showing that inference systems are moving towards more refined workload scheduling.
TPUs and Near-Memory Computing Attempt to Bypass Homogenized GPU Competition
General-purpose GPUs possess mature development models, but not all companies choose to replicate the GPU route.
Zhonghao Xinying showcased the new-generation TPU chip "Xuyu" and the Taize 2.0 server. The chip was released on June 30, and WAIC served as a centralized display. Parameters published by the company show that the "Xuyu" single-chip mixed-precision computing power is 896 TFLOPS, 8-bit inference computing power is 1,792 TOPS, and rated power consumption is 600W. The above data belongs to the company's own metrics and cannot yet be directly compared with GPUs using different precisions and test conditions.
TPUs design dedicated computing units, instruction sets, and data flows for tensor and matrix operations in neural networks. It reduces some general-purpose GPU functions, aiming to achieve higher energy efficiency and more predictable performance under specific AI workloads. The limitations of dedicated architectures are also obvious: when model operators change rapidly, or customers need to run a large number of non-standard workloads, the chip's flexibility and software ecosystem will be tested.
Dongfang Suanxin's DF1000 adopts the route of "software-defined computing + 3D near-memory computing." Public data shows that the chip uses mature domestic processes, achieving vertical stacking through wafer-level hybrid bonding of DRAM and logic chips, with the company announcing a BF16 computing power of 520 TFLOPS. Also displayed alongside the chip are the Tuoyu TY64 super node, server, and cluster solutions.
Near-memory computing targets the "memory wall." The speed at which AI chips execute matrix operations continues to increase, but data still needs to be shuttled back and forth between computing units and VRAM. The time and energy consumed by many workloads lie not in the multiply-accumulate operations themselves, but in data movement.
Placing storage and computing logic closer together through 3D packaging can improve connection density, shorten signal paths, and reduce some data movement costs. However, 3D stacking increases the difficulty of manufacturing, heat dissipation, and yield control. Software-defined architectures also need to prove that their dynamic reconfiguration capabilities can adapt to mainstream models, rather than just completing specific operator demonstrations.
Cloud and Edge Computing Power Are Forming Two Parallel Routes
The large-scale super nodes at WAIC are primarily aimed at cloud data centers, but edge computing power is also rising rapidly.
Axera disclosed the "Yuanxi" series of high-computing-power products at the conference. The enterprise-publicized computing power of the A-series AI inference cards exceeds 1,000 TOPS, targeting high-end edge inference. Since specific precision, power consumption, VRAM capacity, and model tests have not been fully disclosed, it is currently inappropriate to make direct performance comparisons with data center GPUs or other edge chips.
Black Sesame Technologies showcased the Huashan A2000 chip family and the SesameX embodied AI computing platform, extending the automotive-grade computing power originally aimed at intelligent driving to robots and pan-AI devices. Automotive chips need to simultaneously meet real-time performance, functional safety, environmental reliability, and a long lifecycle; these capabilities share certain commonalities with robotic edge computing.
Houmo AI's displayed M50 Inside terminals cover personal smart computing devices, smart offices, robots, and edge inference. Some terminals can already run local large models without a network connection, emphasizing privacy, low latency, and continuous online presence.
The author believes that edge AI will not completely replace cloud models. The more likely form to emerge is edge-cloud collaboration: voice wake-up, real-time perception, motion control, and privacy data are processed locally; complex inference, model training, knowledge updates, and large-scale simulations still rely on cloud super nodes.
The number of terminals is far higher than that of data center servers. Once agents enter PCs, cars, robots, and wearable devices, edge inference chips will form a massive market. However, edge products are more sensitive to power consumption, cost, and memory, and their evaluation criteria also differ from those of cloud GPUs.
Conclusion: System Capabilities Will Determine the Ranking of Domestic Computing Power in the Next Stage
Finally, the key signal released by WAIC 2026 is that domestic AI computing power is moving from single-chip breakthroughs into the system integration stage. The author believes that an increasing number of computing chip manufacturers have acquired productization and engineering capabilities, but to move from prototypes to large-scale commercial deployment, they must still cross five thresholds: delivery, efficiency, software, reliability, and cost.
First, chip yield, advanced packaging, server production, optical modules, liquid cooling, and supply chain capabilities will directly determine whether super nodes can be delivered on schedule. Second, TOPS, TFLOPS, and the number of cards can only reflect theoretical capabilities; training throughput, Time to First Token, Decode speed, cluster utilization rate, and long-term running performance are closer to the customer's actual experience. Software migration costs also cannot be ignored; model adaptation, operator development, performance tuning, and personnel training will all affect the speed at which domestic chips enter customer systems.
As the scale of super nodes expands, link failures, single-card anomalies, and task interruptions will become more common. Capabilities such as link self-healing, fault isolation, breakpoint resume training, and resource reorganization will become important bases for procurement. Ultimately, the market must return to the Total Cost of Ownership: expenditures on chips, networking, liquid cooling, power, server rooms, and O&M will all be reflected in the cost per Token and the energy consumption per unit of business output.
In the future, GPUs, NPUs, TPUs, near-memory computing, and optical interconnects will still coexist in parallel for a long time. Only enterprises that can stably convert peak computing power into model throughput, package complex hardware into user-friendly software platforms, and complete large-scale delivery at controllable costs are more likely to enter the next stage of domestic AI computing competition.