[Relevant Companies Involved in This Article] ASE, Amkor, JCET, TFME, HT-Tech, PTI, Wise Road, Hana Micron, KYE, SJ Semiconductor, Mega Wide, ChipMOS, USI, QZ Technology, Union Semiconductor, China Wafer Level Csp, ECHINT Technology, SiPTORY, Fozhixin Microelectronics, XMC, Tiancheng Advanced Semiconductor, NCAP China, Hsingchen Technology, DF Compute, YMTC, WY Semiconductor, DSHX Technology, Padixon, BIWIN Storage Technology, TSMC, GlobalFoundries, Intel, AMD, Sony, Piotech, NAURA, iSABers, Wisdom Semiconductor, MaxWell, Besi, Adeia, Canon, EVG, STATS ChipPAC, SKC Absolics, Samsung Electro-Mechanics, Sumitomo Chemical, DNP, LG Innotek, BOE, WG Tech (TGVTECH), Lens Technology, Sky Semiconductor, 3D CHIPS (GUANGDONG) Technology, Corning, HGTECH, Innolight, Accelink Technologies, CUMEC.
I. Advanced Packaging Becomes the "Second Growth Curve" for AI Computing Power
Against the backdrop of AI large models continuously driving up computing power demands, the marginal benefits of improving performance solely through transistor scaling are diminishing. The enhancement of computing power is shifting from "transistor scaling" to "packaging integration": 2.5D expands the integration area laterally, 3D shortens data paths vertically, and CPO brings optical interconnects into the package. Consequently, advanced packaging has become the "second growth curve" for AI computing power, with both market and capital curves rising synchronously.
Market side: Yole forecasts that the global high-end performance packaging market will grow from USD 12.1 billion in 2025 to USD 52 billion in 2031, with a CAGR of approximately 27%, among which CoWoS-L-like structures will grow the fastest; by 2031, hybrid bonding revenue will account for 58%, surpassing microbumps to become the primary interconnect method for high-end packaging.
Capital side: Global advanced packaging capital expenditure in 2025 was approximately USD 16.9 billion. Yole expects it to grow by another 40% in 2026, reaching USD 23.8 billion. Note that these are forecasted values, and full-year data still needs to be confirmed after the release of annual reports. Domestically, JCET's capital expenditure budget for 2026 is approximately CNY 10 billion.
Price side: Price hike signals are emerging. According to reports in mid-October 2026, quotations from Taiwanese OSATs such as ASE, KYE, and PTI were generally raised by 10%–30%; ASE increased its 2026 capital expenditure plan from USD 8.5 billion to USD 10.5 billion at its July investor conference.
The main thread of interconnect evolution is the continuous shrinkage of bump pitch. As shown in Figure 2, from the bump pitch of about 140 μm in Flip Chip, to about 40 μm in 2.5D/3D IC, and then to Cu–Cu hybrid bonding at about 10 μm and below in SoIC, each generation of bump pitch shrinkage results in an order-of-magnitude leap in interconnect density.
More importantly, each order-of-magnitude leap in interconnect density requires a material generation shift—microbumps to hybrid bonding, organic to silicon to glass, copper heat dissipation to diamond heat dissipation. This is also the reason why advanced packaging and key materials must be observed together (the key materials part will be expanded in another article).
II. Domestic Advanced Packaging Technology Map: From Bumps and Fan-Out to2.5D/3D, Glass, and CPO
Domestic advanced packaging has formed a full-line layout from bumps and fan-out to 2.5D/3D, glass substrates, and CPO (Co-Packaged Optics). Table 1 sorts out the structural principles, key indicators, domestic representative vendors (platforms), and domestic stages of eight types of technologies from low to high technical levels, among which 2.5D/3D is expanded in Sections IV to VI, and glass substrates and CPO are expanded in Sections VII to IX.
Table 1: Domestic Advanced Packaging Technology Map: Full-Line Layout from Bumps and Fan-Out to 2.5D/3D, Glass, and CPO. Sources: Company announcements, prospectuses, official websites, semi-annual reports, and exhibition materials (as of October 2026); stage judgments are based on public delivery evidence; compiled by ShenXinMeng.
From Table 1, bumps, fan-out, 2.5D silicon interposers, and 3D microbump stacking have entered mass production or mass production ramp-up, with XMC and SJ Semiconductor being the main mass production forces for silicon interposers. In terms of reticle stitching capability, SJ Semiconductor released a 3.3x reticle silicon-based 2.5D solution, and Hubei Hsingchen Technology publicly demonstrated a 4x reticle stitching capability at an exhibition; both belong to capability releases. Hsingchen Technology's silicon interposer (HeteroStar-SIC) was only completed with the Phase II line startup at the end of September and is currently still in the pilot stage.
The only true mass production of hybrid bonding is in storage W2W, represented by YMTC Xtacking and XMC S/M-stacking. Hsingchen Technology launched the HeteroStar advanced packaging process platform with an independent third-party foundry positioning: wafer-level W2W for DRAM plus logic 3D near-memory computing chips, which started risk production shipments in March 2026, but risk production is not yet mass production; chiplet-level D2W (HeteroStar-HIC) has disclosed 200 nm bonding accuracy and <5 μm interconnect pitch, but shipments have not yet been disclosed and it remains under validation. Glass substrates and CPO are in the sampling validation window.
Judgment criteria: Domestically, a 2.5D division of labor has been formed: "front-end silicon interposer by foundries → mid-end bump/TSV exposure by OSATs → back-end assembly and testing"; 3D hybrid bonding is mass-produced first in storage W2W, and computing-storage 3D (Hsingchen Technology) has started risk production shipments, while logic D2W is still under validation. When observing domestic progress, two criteria must be adhered to: "having TSV" does not equal "having self-produced AI interposers"; "risk production" does not equal "mass production".
III. Domestic Landscape: Five Mainland China OSATs Enter Global Top 10 in 1H 2026, Capital Floods into 2.5D/3D
Since the 1H 2026 OSAT ranking from third-party institutions has not yet been released, the list in Figure 3 is self-calculated by ShenXinMeng based on each company's 2026 semi-annual/quarterly reports: ASE only takes the OSAT (ATM) caliber, uniformly converted to USD at the average exchange rate for the first half of the year, and attributed to regions based on headquarters location.
Calculations show that the total revenue of the global top ten OSATs in 1H 2026 was approximately USD 22.50 billion. Mainland China has 5 companies in the top ten: JCET third (USD 2.83 billion), TFME fourth (USD 2.33 billion), HT-Tech fifth (USD 1.52 billion), Wise Road seventh (approximately USD 1.29 billion), and SJ Semiconductor tenth (USD 0.49 billion), accounting for about 37.7% of the top ten revenue in total. Taiwan, China has 3 companies: ASE, PTI, and KYE, accounting for about 42.9% in total, mainly relying on the volume of ASE alone (USD 7.56 billion); US Amkor ranks second with USD 3.58 billion, accounting for 15.9%; South Korea's Hana Micron accounts for 3.6%.
Figure 3: 1H 2026 Global OSAT Revenue Ranking (USD 100 million, by headquarters; right column is YoY growth). Sources: 2026 semi-annual/quarterly reports of each company (ASE takes ATM caliber); *Wise Road is unlisted, estimated by reversing the full-year figure of approximately CNY 17.8 billion according to the 2025 caliber of XinSiXiang, taking half and ignoring growth; converted at the H1 average exchange rate; calculated by ShenXinMeng.
In terms of growth rate, ASE's OSAT revenue increased by 33.1% YoY, mainly driven by AI advanced packaging, with a growth rate higher than that of mainland leading enterprises; HT-Tech grew by 35.1% in the first half of the year, surpassing PTI (USD 1.41 billion, +32.4%) for the first time. JCET grew by 5.0%, TFME grew by 23.0%, Hana Micron grew by 82.7%, KYE grew by 36%, and SJ Semiconductor grew by 7.2%, firmly ranking in the top ten with its mid-end wafer-level capabilities. Outside the top ten, Mega Wide was USD 0.45 billion (+27.1%), ChipMOS was USD 0.39 billion (+17.8%), and USI ranked 13th with USD 0.35 billion (+20.0%), making it the sixth mainland company.
It should be noted that Wise Road is not listed, and its value is estimated by reversing the full-year figure of approximately CNY 17.8 billion according to the 2025 list of XinSiXiang Research Institute, taking half and ignoring growth, which is a conservative caliber; cross-verified with TrendForce's caliber, it is also around the seventh position.
On the capital side, a new round of investment is clearly flowing concentratedly into 2.5D/3D, HBM, and hybrid bonding. As shown in Figure 4, among the key advanced packaging projects in 2026, the Phase I of DSHX Technology Lingang and the Phase I of Hsingchen Technology Industrialization Base both invested approximately CNY 10 billion, tied for first; SJ Semiconductor Jiangyin Phase I was approximately CNY 9.8 billion, and JCET Lingang Base (two phases) was CNY 7.8 billion; Biwin XinCheng HanQi Phase III (proposed) was CNY 4.5 billion, TFME private placement was CNY 4.209 billion, QZ Technology Suzhou 2.5D project was CNY 2.454 billion, Padixon expansion was CNY 1.85 billion, and TianCheng Advanced Phase I (Zhuhai TSV) was CNY 0.95 billion.
In terms of time nodes, SJ Jiangyin Phase I started construction on May 12, and DSHX Technology Lingang Phase I started construction on June 29; Hsingchen Technology Base Phase I started construction at the end of May and broke through the zero level in August, with a planned capacity of 30,000 wafers/month (total base investment of CNY 25 billion); Hsingchen Technology also completed a nearly CNY 5 billion Series A financing this year; TFME's private placement was listed on September 16; JCET's capital expenditure budget for 2026 is approximately CNY 10 billion.
But "starting construction ≠ mass production". From starting construction to forming effective capacity, subsequent tracking of three signals is still required: line startup, customer certification, and yield ramp-up.
IV. 2.5D Principles: TSV Silicon Interposer and Three Interposer Structures
The core of 2.5D packaging is the silicon interposer, which connects logic chiplets and HBM with "micron-level routing + vertical conduction". As shown in Figure 5, its structure from top to bottom is "chip → microbump → RDL → silicon interposer (TSV) → substrate": logic chips and HBM stacks are placed side by side on top of the interposer, enter the top RDL fine routing through microbumps, TSVs then lead the electrical paths vertically to the back of the interposer, and connect to the organic substrate through back-side redistribution and bumps, finally connecting to the system PCB via BGA solder balls.
Referencing TSMC CoWoS, there are three interposer structures, and corresponding domestic platforms have all been deployed:
▸ CoWoS-S | Full silicon interposer: TSV + silicon-based fine lines; 3.3x reticle (approximately 2700 mm²), mass-produced since 2012; the difficulty lies in large-area processing and assembly yield. Domestic counterpart: XMC silicon interposer mass production; SJ SmartPoser-Si large-scale mass production, released 3.3x reticle silicon-based 2.5D solution in August.
▸ CoWoS-R | Organic RDL interposer: replaces silicon with polymer RDL, 4 μm pitch (2/2 μm line width/space); lower cost, the difficulty lies in warpage, copper adhesion, and dielectric loss. Domestic counterpart: JCET XDFOI mass production; SJ SmartPoser-RDL small-volume trial production; TFME VISIONS.
▸ CoWoS-L | RDL + local silicon bridge (LSI): high-density connections concentrated on the silicon bridge; 3.5x reticle, mass-produced in 2024, Yole expects the fastest growth (CAGR 28.1%). Domestic counterpart: SJ SmartPoser-BD full-process validation, 6x reticle silicon bridge completed process development; HT-Tech SiCS.
The value of the interposer lies not in advanced logic nodes, but in high-density routing and signal integrity. Silicon interposers can use mature 65nm processes; the key is deep silicon vias, multi-reticle stitching, and DTC deep trench capacitors. The larger the area, the greater the pressure on warpage, power supply, and yield: TSMC's 5.5x reticle CoWoS is already in production, and 14x reticle is planned for 2028; GlobalFoundries signed a USD 2 billion silicon interposer agreement with TSMC, and the trend of capacity spillover is clear.
V. 3D Integration: From Microbumps to Hybrid Bonding
3D integration is moving from microbumps to hybrid bonding. The principle of hybrid bonding is divided into three steps: the dielectric surface is pre-bonded at room temperature; during annealing, because the metal CTE is greater than the oxide, the copper expands and closes the recessed gaps; after continued heating, the copper is pressed and diffusion-bonded without external pressure, achieving solder-free, bump-free Cu–Cu interconnects.
The mass production benchmark is YMTC Xtacking. The memory array and peripheral CMOS are independently processed on two wafers, and then "merged into one" through millions of metal VIAs via hybrid bonding. XMC's dual/multi-wafer stacking also belongs to the W2W platform and has been mass-produced. Commercial W2W pitch is about 1 μm, and the interconnect density reaches millions/mm².
The three bonding routes have their respective applicable scenarios (Table 2): W2W is mass-produced first in 3D NAND and CIS; D2W is suitable for HBM and logic chiplets, with domestic SJ and NCAP China validating; SAB surface activation is suitable for heterogeneous integration.
Table 2: Three Bonding Routes and Domestic Progress. Sources: imec (IEDM 2023); company announcements; compiled by ShenXinMeng.
A domestic bonding equipment chain has formed an echelon: Piotech Dione 300 (W2W) has received repeat orders, and Pleione (D2W) has reached hundred-nanometer-level precision and has been shipped; NAURA launched Qomola HPD30 (D2W); iSABers focuses on SAB room-temperature bonding; Wisdom Semiconductor and MaxWell are also deploying. In terms of the global landscape, Besi holds about 67% of the hybrid bonding equipment market share, and Adeia holds core patents.
Density transition: TCB microbump pitch shrinks from 40 μm to 10 μm, while hybrid bonding moves from <10 μm to sub-micron, with an interconnect density of 10K–1M/mm² and energy consumption of about 0.05 pJ/bit; Yole expects hybrid bonding to account for 58% of high-end packaging revenue in 2031. Domestic pace: W2W has been mass-produced in 3D NAND and wafer stacking, while D2W is under full-process validation; low-temperature/room-temperature bonding is a key direction to suppress warpage and alignment offset and support heterogeneous integration.
VI. Mass Production Practice: XMC "TSV Full Process" and SJ Semiconductor "2.5D/3D Packaging"
Using the two companies XMC and SJ Semiconductor, we can see the mass production practice of domestic silicon interposers clearly: the former is responsible for "front-end board making" as a foundry, and the latter is responsible for "mid-end integration" as an OSAT.
XMC: Front-end TSV silicon interposer + wafer-level 3D. The front-end process covers deep silicon vias, multi-reticle stitching, DTC deep trench capacitors, and fine copper interconnects, while the mid-end covers thinning and back-side RDL. In August 2026, the company officially confirmed that S-stacking, M-stacking, and 2.5D silicon interposers have all been mass-produced; its third wafer fab has been topped out, planning to add 50,000 wafers/month capacity, covering 3D integration, supporting logic, and RF-SOI.
SJ Semiconductor: SmartPoser-Si eight mid-to-back-end processes. SmartPoser-Si processes from the incoming silicon interposer wafer, sequentially completing eight mid-to-back-end processes such as front-side bumping, wafer back grinding and planarization to expose copper, back-side bumping, die attach, molding, and testing. In the first half of 2026, the company's chiplet multi-chip integrated packaging revenue was CNY 1.828 billion, accounting for 53.66% of revenue; on August 31, it released a 3.3x reticle silicon-based 2.5D solution. In its platform matrix, SmartPoser-Si is in large-scale mass production, SmartPoser-RDL is in small-volume trial production, SmartPoser-BD has completed full-process validation and 6x silicon bridge process development, 3DIC-BP is in mass production, and 3DIC-HB is under full-process validation.
Thus, domestic 2.5D has formed a collaborative division of labor: "front-end silicon interposer (foundry) + mid-end TSV exposure/bumping (OSAT) + back-end assembly and testing". Judgment criteria: "having TSV ≠ having self-produced AI interposers"; 3.3x reticle and 6x silicon bridge belong to capability releases, and specific customer models, batch yields, and shipment volumes still need to be tracked.
VII. Glass Core Substrate: Low Loss, Tunable CTE, Ultra-Flat, Taking Over from Organic Core
Glass serves three distinct roles in advanced packaging: temporary glass carriers, glass interposers/routing layers, and glass-core package substrates. This article focuses on the third application: replacing the organic core substrate used in FC-BGA packages with a glass core, with through-glass vias (TGVs) providing vertical (Z-direction) electrical interconnections.
The advantages of glass can be summarized as "low loss, tunable CTE, ultra-flat, panel-level": the dielectric loss Df at 10 GHz is only 0.001–0.003, which is beneficial for high-speed signals; the CTE is tunable between 3–8 ppm/K, close to silicon, which can suppress large-size warpage; the surface is ultra-flat, with RDL line width/space reaching 2/2 μm and inter-layer alignment <±1 μm; it can be processed at the panel level on 510×515 mm panels, with high area utilization. The shortboard is that thermal conductivity is only 1.1–1.4 W/m·K (silicon is about 150).
The same-size test vehicle (TV) comparison published by STATS ChipPAC at ECTC 2026 (Table 3) provides intuitive evidence: under the same configuration of a 74×74 mm package with 2 25×25 mm chips and 6 15×10 mm memories, after switching from an organic core to a glass core, the substrate layers decreased from 14 to 8 (−43%), the total thickness decreased from 1.81 mm to 0.92 mm (−49%), and the via hole diameter decreased from 150 μm to 90 μm (−40%). The glass core nearly halves the layers and thickness.
Table 3: Same-Size Test Vehicle: Glass Core Nearly Halves Layers and Thickness. Sources: STATS ChipPAC ECTC 2026 paper test vehicle (published by SemiAnalysis, not mass production specifications); compiled by ShenXinMeng.
Value: Low loss + CTE matching + ultra-flat + panel-level, simultaneously alleviating the three bottlenecks of warpage, routing density, and high-speed signals in ultra-large packages, adapting to AI/HPC chips above 2x reticle. Challenges: brittleness and cutting micro-cracks, TGV metallization adhesion, low thermal conductivity, and matching with the build-up and assembly ecosystem—this is precisely the opportunity for domestic materials and equipment to切入.
VIII. Glass Substrate Industrialization: International Sprint to Mass Production, Domestic Enters Sampling and Small-Batch Window
International: Trial production starts in 2026, mass production ramp-up from 2027–2029 (Table 4). Intel showcased the industry's first 10-2-10 thick glass core + 2 EMIB silicon bridge solution at NEPCON 2026; SKC Absolics' Georgia, US factory started production this year; Samsung Electro-Mechanics plans to mass-produce in the second half of FY2027; TSMC CoPoS is expected to mass-produce in 2028–2029; DNP and LG Innotek's nodes are around 2028.
Table 4: International Glass Substrate Industrialization Progress. Sources: Intel NEPCON 2026; Samsung Electro-Mechanics, DNP announcements; The Elec; compiled by ShenXinMeng.
Domestic: Panel-level processes have been run through, entering customer sampling and small batches (Table 5). BOE's trial line was started in the first half of this year, with a mass production decision in 2027; Woge has delivered small batches; Sky Semiconductor's wafer-level TGV has cumulatively shipped over20,000 pieces; Lens Technology and 3D Graphene/Fozhixin Microelectronics are in the pilot and R&D-to-small-batch transition stages, respectively.
Table 5: Domestic Glass Substrate Industrialization Progress. Sources: BOE, Woge Optoelectronics, Lens Technology announcements and semi-annual reports; "Observation on Glass Substrate Technology, Die Attach, and Delivery in the First Three Quarters of 2026"; compiled by ShenXinMeng.
Timeline convergence: International leaders trial-produce in 2026 and ramp up mass production from 2027–2029; domestic BOE, Woge, Lens, etc., have completed panel-level process run-throughs, with a gap of about 1–2 years compared to international levels. Rational judgment: "having TGV samples ≠ entering die attach supply"; the key is OSAT die attach, reliability (reflow/thermal cycling/damp heat), and continuous delivery, with large-scale application expected in 2028–2030.
IX. Co-Packaged Optics (CPO): Glass Substrates "Carry Both Electricity and Light"
Another value of glass is "carrying light". CPO pulls the optical engine from the panel into the package, shortening the electrical channel to the millimeter level, and reducing power consumption by 50%–70% compared to pluggable optical modules. Glass is transparent, low-loss, and can be directly made into waveguides, making it an ideal carrier for the integration of "electrical interconnect + optical interconnect". Currently, there are two routes, and silicon photonics and IOX waveguides are moving towards fusion.
Route A: Silicon Photonics CPO—SOI waveguides carry light, glass/organic substrates only carry electricity. The optical path is "optical fiber → FAU → SOI waveguide → Ge detector → microbump → EIC". FAU active alignment takes >5 min per chip, with a yield of <60%, which is a bottleneck for scaling.
Route B: Glass Optoelectronic Fusion—TGV carries electricity + IOX glass waveguide carries light. The optical path is "optical fiber → IOX fan-in → 45° reflector → PIC", with an end-to-end loss target of ≤2.5 dB; representative solutions include Corning GlassBridge and Intel glass coupler .
Table 6: CPO Key Indicators. Sources: "Research Report on the Integration of Glass Substrates and Silicon Photonics Industry Chain"; compiled by ShenXinMeng.
Domestic progress: HGTECH, Innolight, Accelink, and CUMEC are promoting optical engines and silicon photonics platforms; JCET and TFME are deploying CPO packaging; Hsingchen Technology has also completed preliminary validation of a complete set of CPO processes on its pilot platform. Material bottlenecks are concentrated in SOI wafers, IOX glass, and precision coupling.
X. Summary and Outlook: Domestic Progress, Three Judgments, and 2026–2030 Key Nodes
Placing the above platforms in the same domestic matrix (Table 7): 2.5D silicon interposers, 3D microbumps, and storage W2W hybrid bonding have been mass-produced; Hsingchen Technology's silicon interposer was just completed in Phase II and is still in pilot; 2.5D RDL/silicon bridges are in small-volume trial production. The representative for the DRAM-Logic computing-storage 3D row is Hsingchen Technology: it completed mass production validation for DF Compute DF1000, started risk production shipments in March 2026, and Phase II line startup at the end of September; but risk production is not yet mass production, and the platform will not reach full production until the first quarter of 2027. D2W, glass cores, and CPO are under validation or sampling; Hsingchen Technology has disclosed 200 nm bonding accuracy for D2W, and the complete set of CPO processes has also completed preliminary validation.
Table 7: Domestic Advanced Packaging Platform Domestic Stage Matrix. Sources: Company announcements, prospectuses, and semi-annual reports; industry research and exhibition materials; stage judgments are ShenXinMeng's evaluation based on public information, as of October 2026.
Table 8: 2026–2030 Key Node Outlook (Including Expectations). Sources: Previous sections; Yole; company announcements; time nodes include public plans and ShenXinMeng expectations, for reference only.
Domestic advanced packaging has moved from "whether it can be done" to the stage of "yield, cost, and customer introduction". A new generation of AI packaging paradigm of "glass-based CPO + diamond heat dissipation" is expected to form around 2028. Based on the above review, we give three judgments:
Judgment 1 | Platform: 2.5D/3D enters "mass production + ramp-up". SJ Semiconductor's 2.5D revenue accounts for over half, and XMC's wafer-level 3D has been mass-produced; the next step is the yield ramp-up and customer introduction for 3.3x+ reticle interposers, silicon bridges, and D2W hybrid bonding. Keywords: Yield · Capacity · Customer Introduction.
Judgment 2 | Materials: From "single-point substitution" to "system synergy". Plating solutions, bonding dielectrics, SOI, special glass, and diamond must be jointly validated with equipment and processes; the winning hand for domestic materials lies in purity, batch consistency, and OSAT certification cycles. Keywords: Purity · Consistency · Joint Validation.
Judgment 3 | Frontier: Triple fusion of glass + light + heat. The glass core substrate simultaneously carries TGV electricity and IOX light, and diamond breaks the kilowatt-level thermal wall;
References:
[1] Yole Group. (2026). High-End Performance Packaging 2026. Yole Intelligence.[2] Yole Group. (2026). Status of the Advanced Packaging Industry 2026. Yole Intelligence.[3] ASE Technology Holding. (2026). ASE Technology Holding Co., Ltd. Reports Its Unaudited Consolidated Financial Results for the Second Quarter of 2026. PR Newswire.[4] Domestic Advanced Packaging & Key Materials: Frontier Technology Highlights and Industry Outlook-ppt-Lu Bing, China Semiconductor Industry Insight Forum. (2026-10-16).