[Relevant Companies Mentioned in This Article] ASE, TSMC, Nvidia, ECTC, GF, SMIC, Innoscience.
Mature Packaging > Novel Process Nodes
At the recently concluded OCP APAC 2026 summit last month, CP Hung, Senior Vice President of ASE, delivered a highly substantive keynote titled "Advanced Packaging: Enabling AI at Scale." He not only broke down advanced packaging into a 'trilogy' of electrical, optical, and power domains, but also further demonstrated how panel-level packaging addresses throughput bottlenecks, how Co-Packaged Optics (CPO) solutions tackle bandwidth and power consumption, and how embedded power delivery resolves efficiency challenges. In the field of CPO, the competitive dimension of packaging has shifted from 'who has the strongest optical design' to 'who has the most mature system-level packaging.' The industry trend is no longer about inventing new process nodes, but rather rearranging existing technologies to achieve the best possible results.
To understand this shift in industry trends, one must first look at the foundation ASE has for CPO: the VIPack platform. Covering FOPoP, FOCoS, FOSiP, 2.5D/3D IC, all the way to FOCoS-Bridge and CPO, it was launched in June 2022. Positioned as ASE's next-generation 3D heterogeneous integration architecture, it utilizes RDL + embedded integration + 2.5D/3D technologies to cover everything from mature packaging to cutting-edge system-level packaging. Industry-leading packaging specifications include: a die-to-die pitch of 50um for chiplets; 6P6M RDL layers capable of accommodating passive components with inter-layer copper pillars 150 micrometers high; stress-relief vias integrated within TSV packaging; as well as ultra-low loss interconnects and hybrid bonding capabilities.
ASE's presentation was straightforward. While each individual technology may not seem to be the absolute most advanced on its own, combining them enables a 120×120 mm package to simultaneously accommodate an XPU, HBM, and an optical engine. Essentially, CPO does not require inventing a brand-new process node; rather, it involves rearranging, combining, and optimizing mature packaging technologies. FOCoS-Bridge is a typical example. Its interconnect density can be dozens of times higher than that of traditional FCBGA, achieved by embedding a small silicon bridge in areas requiring high-density interconnects. 2.5D packaging combined with a Si interposer can achieve a pitch of around 0.5um, while the remaining areas are handled by RDL copper layers. Meanwhile, the fan-out RDL in FOCoS alone can achieve varying pitches from 2um to 10um. This flexible approach of deploying high density wherever needed transforms the previous 'one-size-fits-all' approach of using a single technology for a single package into a multi-technology strategy of 'targeted attacks and zone-specific optimization.'
Overcoming Physical Limits
ASE's recognition of CPO and its technical feasibility demonstration are already quite comprehensive. In April 2025, the officially demonstrated CPO device achieved a power consumption of <5 pJ/bit. As it now moves towards full-scale mass production, ASE has also communicated to the industry the three major mountains it is about to face: warpage, coupling, and thermal management.
First is warpage control. As packages become thinner and larger, the CTE (Coefficient of Thermal Expansion) mismatch among internal materials increases, exacerbating package warpage. In ASE's CPO packaging process, controlling substrate warpage and coplanarity is a prerequisite for meeting the coupling requirements of fiber arrays. The coupling alignment of fiber arrays requires sub-micron precision; a substrate warpage of tens of micrometers means alignment failure. To address this, ASE's solution combines TCB (Thermocompression Bonding) with stress-relief via designs, temporarily alleviating this industry challenge through process-level stress compensation.
The second challenge is fiber array coupling. The industry is still at a tug-of-war between detachable and non-detachable solutions. ASE's view is that 'the industry currently still prefers detachable solutions,' so it leans towards a top-side coupling + wafer-level packaging approach for coupling. CP also introduced that with this approach, coupling accuracy relies more on the alignment of wafer-level equipment. Many existing HBM and TSV stacking packaging equipment can be repurposed for this. However, a new bottleneck has emerged here: the equipment and standards for wafer-level optical testing are still immature and urgently need to be overcome.
Finally, there is thermal management. In CPO packaging, the optical engine is placed very close to the ASIC. The computing chip generates massive amounts of heat. Silicon has a high thermo-optic coefficient; a change in temperature causes the refractive index to drift, which in turn shifts the microring resonance peak. AMD's solution is to place micro-heaters and control circuits next to the microring modulators for closed-loop compensation, but this only treats the symptoms, not the root cause. ASE, on the other hand, focuses on the more macroscopic thermal management issue. In system-level packaging, the thermal densities of the optical engine, ASIC, and HBM differ, leading to ununified and mutually interfering thermal dissipation paths. ASE is currently exploring microchannel cooling and tin-based material solutions, but there is still a distance to go before mass production validation.
ASE summarized a highly accurate commonality among these three major physical obstacles: it is not a question of whether it can be done, but whether it is practical and usable once done. Yield, throughput, and cost are all top priorities that must be considered at every level.
Power Efficiency Is the Real Focus
CP Hung also spent considerable time discussing the power delivery aspect, which many manufacturers tend to overlook. He presented a logical framework: starting from the power grid, the power loss from high-voltage grid supply to the low-voltage household side, and then through transformers to the chip level, starts at a minimum of 10%. The power consumption of computing centers often reaches millions of watts; even a 0.5% improvement translates to massive savings in electricity costs and thermal management (which explains why top global computing companies are building their own power plants or nuclear reactors).
On the packaging integration side, he also outlined several directions: integrating SMD passive components with multi-layer substrates to reduce trace losses; embedding power ICs and inductors directly into the substrate; and using wafer-level RDL to create double-sided, smaller-sized high-voltage power delivery paths. The core idea is simply to integrate discrete power delivery components into the package itself. This development path has a clear technical name: Vertical Power Delivery (VPD).
The concept of VPD was first proposed by Vicor at DesignCon in 2019. Its core logic is to place the power module directly beneath the processor package, delivering power vertically through the PCB or substrate, shortening the power delivery path from the centimeter level to the millimeter level. In September 2025, Yuanbao servers demonstrated their self-developed multi-phase vertical power delivery architecture, increasing the power delivery capability for AI chips to over 1000A, shortening the power delivery path by 60%, and reducing transmission losses by 66%.
CP Hung also mentioned the 800V high-voltage modules outside the package, which represent another major trend. The currently mature 800V DC architecture, a collaboration between Innoscience and NVIDIA, utilizes its third-generation GaN (Gallium Nitride) technology. On the 800V input side, compared to silicon carbide, it reduces driving losses by 80% and switching losses by 50% per switching half-cycle, resulting in a 10% reduction in overall power consumption.
Conclusion
Returning to CP Hung's trilogy framework, the three parts are not parallel but sequential. Panel-level packaging advances mass production, CPO's co-packaged optics unlocks bandwidth, and finally, embedded power delivery further reduces power delivery losses. The entire presentation was packed with substantive insights. The industry's focus is no longer on a single new technology, but on the integration capability of existing technologies. The core competition for AI computing chips has shifted from 'who has the more advanced process node' to 'who can integrate optics and electronics well while still achieving mass production.'
References:
"2026 OCP APAC Summit | The Next Battleground for AI Hardware Is Not in Manufacturing Processes, But in Packaging: Deconstructing ASE CP Hung's 'Integration Trilogy'"
#DeepChipAlliance #BayChipExpo #SemiconductorIndustryResearch #Co-PackagedOptics #CPO #Packaging #ASE