As intelligent vision applications rapidly evolve from merely "seeing" to truly "understanding," the computing power density, energy efficiency, and response latency of edge chips have become the core bottlenecks restricting real-world scenario deployment.
To address this industry pain point, at the 5th Dishui Lake China RISC-V Industry Forum held today, Huang Shaorui, General Manager of the Product R&D Center at Allwinner Technology Co., Ltd., introduced a high-performance network camera processor—the V861.
Figure | Huang Shaorui, General Manager of the Product R&D Center at Allwinner Technology Co., Ltd.; Source:VeriSilicon
Huang Shaorui pointed out that based on the open RISC-V architecture, the V861 provides a highly energy-efficient solution for 4K-level intelligent vision processing through the collaborative design of heterogeneous computing units and dedicated image acceleration engines.
Heterogeneous Computing Architecture Reshapes Energy Efficiency Boundaries
Instead of following the conventional application processor route dominated by Arm, the V861 adopts a heterogeneous solution featuring a dual-core 64-bit RISC-V processor (Xuantie C907) paired with an independent MCU (E907).
Figure | Product Introduction of the V861 Smart Vision-Specific Chip; Source: Allwinner Technology
The main core supports the RVA22 instruction set specification and RVV1.0 vector extension. Operating at a 1.4GHz clock frequency, it can efficiently handle audio and video codec scheduling and complex AI pre-processing tasks. Meanwhile, the MCU focuses on real-time control in low-power scenarios, enabling millisecond-level cold starts for sensor image output and screen display.
Huang Shaorui believes that this clearly divided architectural design allows the chip to maintain a compact form factor with 64MB/128MB built-in DDR in a QFN88 (9mm×9mm) package while providing 1TOPS INT8 NPU computing power, making it particularly suitable for wearable devices sensitive to PCB area.
End-to-End Intelligence of the Image Pipeline
Unlike the approach of simply stacking ISP units, the AI-ISP of the V861 integrates the neural network's ability to understand scene semantics. In low-light environments, its newly upgraded ISP algorithm can leverage the 1TOPS computing power of the NPU for real-time noise reduction and color restoration, significantly reducing the smearing effect of traditional ISPs on dark details.
The video encoding unit supports dual-standard hardware encoding for H.265/H.264, enabling dual-channel concurrent output of up to 4K@25fps + 720P@25fps.
The flexible combination of three MIPI-CSI channels (configurable as 1×4-lane/2×2-lane/3×1-lane) allows the simultaneous connection of multiple sensors, including wide-angle, telephoto, and infrared, providing a hardware foundation for panoramic monitoring or binocular stereo vision.
Engineering Implementation of Edge Intelligence
For compute-intensive tasks such as edge EIS (Electronic Image Stabilization), fisheye unwarping, and distortion correction, the V861 avoids resource contention on general-purpose cores through the collaborative division of labor between the image accelerator and the NPU.
Huang Shaorui believes that this model of "using dedicated engines to handle deterministic loads and programmable NPUs to address scenario-specific algorithms" demonstrates advantages in fields such as smart door locks and dashcams, which require a balance between real-time performance and algorithm iteration.
Figure | Main Applications of the V861 Smart Vision-Specific Chip; Source: Allwinner Technology
In addition, with the AI development workstation provided by Allwinner, developers can quickly deploy trained vision models to the NPU, thereby shortening the engineering cycle from algorithm to product.
Figure | Allwinner's One-Stop AI Development Workstation; Source: Allwinner Technology
At the end of the presentation, Huang Shaorui emphasized that from 4G HD IPCs in smart security to lightweight visual interaction in AI glasses, the V861 demonstrates a critical leap of the RISC-V architecture in the dedicated vision field from "usable" to "user-friendly"—not relying on aggressive advancement in process technology, but seeking the optimal solution for commercialization within the triangular constraints of power consumption, cost, and computing power through architectural innovation and deep integration with vertical scenarios.