As the miniaturization of front-end wafer processes approaches physical limits, the R&D costs for single-wafer miniaturization technologies are rising exponentially, and the marginal benefits of front-end Moore's Law are diminishing. Against this backdrop, extending the growth of computing power through back-end packaging technology innovation—the 'back-end Moore's Law'—has become a critical path for enhancing semiconductor performance in the post-Moore era.
Global IC (Integrated Circuit) packaging technology has undergone five development stages to date. The first three stages belong to traditional packaging, primarily characterized by wire bonding and through-hole insertion. The fourth and fifth stages have stepped into the era of Advanced Packaging, represented by flip-chip, wafer-level packaging, System in Package (SiP), Through-Silicon Via (TSV), and 3D stacking.
In 2025, the global packaging and testing industry ushered in a historic 'handover moment.' Behind this lies a life-and-death breakthrough battle featuring close-quarters combat between domestic equipment manufacturers and international giants.
2025: The Packaging Handover Crossing a Historical Watershed
The leap from traditional packaging to Advanced Packaging is being accelerated by the explosive growth of data centers, AI (Artificial Intelligence) computing power, and smart vehicles. The industry has reached a landmark milestone:
A report by Yole Group shows that in 2025, the global Advanced Packaging market size reached approximately $53.1 billion, a year-on-year growth of 9.6%. Its share exceeded traditional packaging for the first time, reaching 51%, marking the official entry of global packaging technology into an era dominated by Advanced Packaging. By 2030, the global Advanced Packaging market size is expected to reach $79.4 billion, with a CAGR of approximately 8.4%.
In the Chinese mainland market, the urgent demand for computing power autonomy and supply chain security has generated higher growth elasticity.
Surging Market Growth: Based on aggregated statistical data from various institutions, the forecast range for the domestic Advanced Packaging market size in 2025 is mainly concentrated between RMB 85 billion and RMB 110 billion, with a CAGR of up to 19.2% from 2024 to 2030.
Massive Dividend from Penetration Rate: In 2024, the penetration rate of Advanced Packaging in the Chinese mainland was approximately 40%, still lower than the global average of 55%. This generational gap of nearly 15 percentage points precisely provides a 'golden frontier' with immense mid-to-long-term penetration value for domestic packaging and testing giants and local equipment manufacturers.
Driven by this process evolution, mid-end ultra-thin process equipment is experiencing rigid explosive growth. Bonding, thinning, and dicing are becoming the three most dazzling golden tracks for the domestic substitution of equipment.
Three Core Equipment Tracks: The Hardcore Leap of Domestic Equipment Manufacturers
Bonding Equipment: The Ultimate Game of Nanometer-Level Alignment and Atomic-Level Interconnection
The bonding process is the core of achieving high-density vertical interconnection. Its technological roadmap evolves progressively along 'Thermocompression Bonding (TCB), Temporary Bonding and Debonding (TBDB), and Hybrid Bonding.'
1. Temporary Bonding and Debonding: The 'Safety Belt' for Ultra-Thin Wafers
As the number of chip layers stacked increases and thickness decreases, ultra-thin wafers are highly susceptible to cracking and deformation. The TBDB process provides mechanical support by bonding the device wafer to the carrier wafer using a temporary medium, followed by lossless separation after backside metallization is completed.
Domestic Breakthrough: Kingsemi has launched temporary bonding/debonding equipment specifically tailored for thick photoresist/bonding adhesive processes (greater than 60μm). Compatible with mainstream materials, it has seen surging orders from multiple major manufacturers. Maxwell developed the MX-21D1 fully automatic temporary bonder, featuring an innovative design of 'one pre-bonding chamber supporting two bonding chambers,' which improves system efficiency by 60% and can accommodate highly deformed wafers with a warpage of up to 5mm.
2. Hybrid Bonding: Bumpless Interconnection at the Physical Limit
As the 'standard' technology for next-generation ultra-high bandwidth HBM and 3D SoC (System on Chip), hybrid bonding directly eliminates traditional micro-bumps. It achieves surface fusion of dielectrics such as silicon dioxide at room temperature, followed by annealing to induce atomic-level diffusion interconnection of copper contacts. Its alignment accuracy requirements have entered the sub-micron or even nanometer level.
Domestic Breakthrough: Piotech, leveraging the technological synergy of front-end thin films and surface vacuum plasma treatment, has its Dione 300 W2W (Wafer-to-Wafer) equipment validated by customers and reordered in 2023. Its Pleione 300 C2W (Chip-to-Wafer) equipment has also entered the fields of HBM and 3D chip integration for validation and shipment. In 2025, Piotech's hybrid bonding equipment revenue surged by 41.92% to RMB 136 million, taking the lead in closing the commercialization loop. Meanwhile, Maxwell delivered its first wafer-level hybrid bonding equipment in May 2025, achieving an alignment accuracy of ±100 nm level and launching an assault on the international highest standard of ±50 nm.
Thinning Equipment: Precision Reconstruction on the 'Tip of the Blade' at the Hundred-Micrometer Level
Vertical stacking processes require wafers to be thinned to the tens-of-micrometers level (as thin as cicada wings). However, pure mechanical grinding leaves micro-cracks and a damaged layer on the surface, necessitating the highly integrated combination of mechanical grinding and CMP (Chemical Mechanical Polishing) processes. Because it directly relates to the survival of ultra-thin wafers worth tens of thousands of dollars each, the technology for integrated thinning equipment has long been highly monopolized by Japan's Disco.
Domestic Breakthrough: HWATSING, incubated by Professor Lu Xinchun's team at Tsinghua University, has captured approximately 50% of the domestic 12-inch CMP market. Building on its profound CMP process accumulation, HWATSING launched the first 12-inch ultra-precision wafer thinning and polishing integrated machine Versatile-GP300, which has been sent to the production lines of domestic IC leaders for validation. By eliminating surface damage through highly integrated grinding and polishing, this equipment directly cuts into the monopoly hinterland of high-end ultra-thin processes. Furthermore, since direct materials account for over 90% of its costs, the localization space for local component supply chains leaves immense room for imagination in domestic industrial synergy.
Dicing Equipment: The Market Migration Towards Fine Laser Cutting
Given the extensive use of Low-k (low dielectric constant) materials and the extreme thinning of wafers, traditional mechanical blade dicing is highly prone to causing severe chipping and mechanical stress damage. The process path is accelerating its shift towards Stealth Dicing—which focuses ultrafast lasers inside the wafer to form a modified layer, and then stretches it to achieve stress-free, dust-free, and chip-free natural fracture of the chips.
Domestic Breakthrough: In high-end mechanical dicing, Guangli Technology has thoroughly controlled the lifeline of high-end dicer bases—high-precision semiconductor air spindles—through the acquisition of UK-based LP and Israel-based AMT. Its multi-blade mechanical dicers have successfully penetrated leading domestic and international packaging and testing companies, breaking Disco's absolute monopoly. In the field of stealth laser dicing, local laser giants such as Han's Laser and DeLong Laser, relying on independent optical path design and multi-band light source integration, have achieved large-scale delivery of domestic equipment in silicon-based ICs and compound semiconductors such as SiC and GaN.
Emerging Scenarios: Glass Substrates and Panel Level Packaging (FOPLP)
Beyond the in-depth exploration of silicon-based materials, the industry is undergoing a revolutionary evolution towards larger physical scales and non-wafer media:
1. 'Vitrification' of Substrates—The Dividend of TGV (Through-Glass Via) Hole Formation
To overcome the thermal shrinkage and warpage losses of traditional ABF substrates in large-size chips, glass substrates, with their high flatness, low coefficient of thermal expansion, and extremely low high-frequency signal loss, have become the ultimate alternative carrier for vertical interconnection of large-size computing chips.
Its core increment lies in TGV laser drilling equipment. Domestic DeLong Laser is excellently positioned in this forward-looking technology, and its ultrafast laser micro-nano precision processing capabilities will directly capture the technological dividends of this explosive track.
2. Panel Level Packaging (FOPLP)—Efficient Cost Reduction Through Large-Area Restructuring
FOPLP technology, which restructures chips on 600 mm × 600 mm square panels, boasts a much higher area utilization rate than round wafers. Its significant cost-reduction effect in mass production has attracted heavy investments from packaging and testing foundry giants such as TSMC (Taiwan Semiconductor Manufacturing Company) and ASE (Advanced Semiconductor Engineering).
However, large-area square substrates face severe pain points of warpage and thermal deformation. This has bred high-premium opportunities on the equipment side: for instance, the need for lithography equipment to possess extremely high dynamic alignment and pattern compensation algorithms, and large-area electroplating equipment to achieve ultra-high uniformity electrodeposition, is rapidly supporting a brand-new multi-billion-level equipment sub-track.
Massive Expansion by Domestic Packaging and Testing Leaders Enables Closed-Loop Growth of Domestic Equipment
Advanced Packaging is a highly complex art of non-standardization and customization. Especially in cutting-edge processes like hybrid bonding and ultra-precision grinding, equipment manufacturers cannot advance a single step by fighting alone.
Currently, the two domestic packaging and testing giants—JCET (planning capital expenditures of RMB 10 billion in 2026) and TFME (the main packaging and testing partner for AMD, with Advanced Packaging revenue accounting for up to 70% and facility investments reaching RMB 9.1 billion)—are heavily tilting their heavy-asset expenditures to urgently build a local supply security net.
By establishing 'joint R&D laboratories' among packaging and testing giants, foundries, and equipment leaders such as Piotech, Maxwell, HWATSING, and Kingsemi, and conducting joint non-standard research in a trinity of 'equipment + materials + process design,' domestic Advanced Packaging equipment has truly entered a virtuous cycle of 'validation—volume ramp-up—reordering—circle expansion.'
Summary
At the historical turning point in 2025 when Advanced Packaging exceeds 50% for the first time, Chinese semiconductor equipment manufacturers are leveraging mid-end ultra-thin processes as a lever to reconstruct the golden foundation of the entire local chip industry chain.
#Shenxin Alliance #Bay Area Chip Exhibition #Semiconductor Industry Research #Advanced Packaging