According to reports from the South Korean semiconductor media The Elec, Samsung Electro-Mechanics (SEM) is collaborating with Qualcomm to develop a 2.1D heterogeneous integration advanced packaging solution for AI chips. Both parties have been conducting R&D and reliability certification for this technology platform for over a year.
The core innovation of this 2.1D packaging solution is the use of an embedded organic bridge. The technical architecture is similar to Intel's EMIB (Embedded Multi-die Interconnect Bridge) technology, but it abandons the silicon bridge used in the EMIB solution, opting instead for organic materials commonly used in the PCB (Printed Circuit Board) field to create the bridge structure. The organic bridge is essentially a micro-substrate integrating 5 to 7 layers of RDL (Redistribution Layer) routing. It targets a line width and spacing of 1.5 to 2 microns, a via size of 4 to 5 microns, and can achieve a routing pattern density of 500 to 1,000 lines per millimeter, building high-speed interconnect channels between chiplets.
The organic bridge has become a new move in the game of advanced packaging. To understand its position, we must first return to the problem itself: what exactly is advanced packaging solving, and which manufacturers are currently in the spotlight.
Simply put, the problem advanced packaging aims to solve is this: as AI chips grow larger, a single die is constrained by the reticle size limit and cannot be made any bigger. Manufacturers have to split a large chip into multiple "chiplets" (dies) and then package them together.
The challenge is that chiplets must be connected with extremely high-density routing to achieve sufficient bandwidth. The denser the connections, the higher the cost and process difficulty. Whoever can connect the dies in a more cost-effective way will secure a ticket to the next phase of AI chips.
Currently, the following approaches are in the spotlight.
1. TSMC's CoWoS
TSMC (Taiwan Semiconductor Manufacturing Company)'s packaging portfolio is centered around CoWoS, spinning off into models such as CoWoS-S (silicon interposer), CoWoS-R (RDL interposer), and CoWoS-L (hybrid solution). The underlying logic is to place an interposer under the chip and achieve global high-density interconnection through TSVs (Through-Silicon Vias).
CoWoS-S uses a full silicon interposer to connect the GPU and HBM via TSVs. It is the solution with the highest performance ceiling, and NVIDIA's accelerators from H100 to H200 all follow this path.
CoWoS-R switches to an organic RDL interposer, which costs less than the silicon solution. It is used for products with slightly lower bandwidth requirements, such as NVIDIA's Vera CPU.
CoWoS-L is a hybrid of the two: it embeds small Local Silicon Interconnect (LSI) blocks on an organic RDL interposer. This supports ultra-large packaging areas while retaining the high-density interconnection capability of silicon. NVIDIA's flagship accelerators from Blackwell to Rubin are all tied to this process.
The common technical core of the three models is the 2.5D architecture of "placing an interposer under the chip and using TSVs for global interconnection." The larger the interposer, the more dies it can hold, but material and yield costs also surge with the area. This is the unavoidable contradiction between performance and cost in CoWoS, and also the gap where other approaches can enter.
Beyond CoWoS, TSMC also has SoIC, which belongs to the 3D stacking route: it vertically stacks dies using hybrid bonding, without going through bumps and interposers in the middle, resulting in a higher inter-die interconnection density than 2.5D.
In August, TSMC Vice President He Jun stated that CoWoS with a 5.5x reticle size has entered mass production, with yields stably exceeding 98% across products from multiple AI customers, and even reaching 99% in some cases. TSMC will also maintain the pace of launching new technologies every year, and is expected to expand CoWoS to a 14x reticle size by 2029.
According to media reports, TSMC's advanced packaging CoWoS capacity is in short supply, with orders fully booked up to 2027. Some customers even have to wait over a year to secure an order. Rumor has it that some backend advanced packaging orders have overflowed to Intel's Malaysia plant, providing capacity cooperation to serve common major customers, breaking past ecosystem conventions.
2. Intel's EMIB
Given the ongoing supply bottleneck at TSMC, Intel's new technology is gaining attention as an alternative solution.
Intel's EMIB takes a different approach: instead of laying a full interposer, it embeds a small silicon bridge only where the die requires high-density connections, placing the bridge exactly where needed. This concept replaces the full interposer with a local bridge, saving the material and yield costs of large-area silicon interposers, and bypassing the physical constraints of CoWoS at large areas.
However, EMIB has a shortcoming: the bridge is only responsible for signal interconnection, and power delivery becomes an issue as chips grow larger. When the die area exceeds the reticle size by several times, power must travel a long path to supply the die, and voltage drop and power loss will eat into the performance advantages.
To address this issue, Intel introduced EMIB-T, which incorporates TSVs into the bridge, allowing power to be supplied directly to the die vertically from the bottom of the package through the bridge, significantly shortening the power delivery path. This technology was officially unveiled at the 2026 IEEE ECTC conference: the test vehicle packed chips with over 9x the reticle area into a package exceeding 120x120 mm, with the inter-die interconnect bump pitch reduced to 25 microns.
According to the roadmap in Intel's official platform briefing, EMIB-T plans to achieve over 8x the reticle size by 2026, and over 12x by 2028, with a package size greater than 120x180 mm, capable of accommodating more than 24 HBMs.
According to reports, Intel's EMIB-T advanced packaging technology has achieved a yield breakthrough of over 90%, and mass production is expected to begin next year, with costs only half of TSMC's CoWoS.
It is reported that MediaTek officially announced in a recent earnings call that it plans to adopt both CoWoS and EMIB-T technologies to develop AI ASICs (Application-Specific Integrated Circuits) on a large scale. Broadcom and Meta are also considering transitioning from CoWoS to EMIB to reduce costs, while Google and NVIDIA have shown strong interest in EMIB-T.
3. Samsung's Vertical Integration
Samsung Foundry's advanced packaging previously used the names I-Cube and X-Cube. I-Cube S was the silicon interposer solution, I-Cube E was the embedded silicon bridge solution, and X-Cube corresponded to 3D stacking. Later, these technologies were integrated into the Cube series and renamed according to the "dimension + letter" format.
The 2.5D Cube-S corresponds to the original silicon interposer route; the 2.3D Cube-E is a silicon bridge embedded structure, which embeds finely patterned silicon bridges on a TSV-less RDL interposer, and then combines FO-PLP (Fan-Out Panel-Level Packaging) to achieve large-area packaging. The concept is similar to Intel's EMIB, but uses panel-level processes to scale up the area. The 2.3D Cube-R takes a pure RDL interposer route without using silicon, focusing on low-cost heterogeneous integration. Moving up, there are also 3D Cube-T/H, which use TCB (Thermocompression Bonding) and HCB (Hybrid Copper Bonding) respectively for vertical die stacking.
Samsung's differentiation lies in its vertical integration: substrates are supplied by Samsung Electro-Mechanics, packaging is completed by the foundry business, HBM is produced in-house, and it also has its own fabs for logic chips. The entire chain from design to packaging is kept within the system, making it unique among the three.
A September report by The Elec mentioned that Samsung Electronics Foundry is expected to conduct packaging performance and reliability evaluations on Samsung Electro-Mechanics' organic bridge substrates. If this path is successfully established, Samsung's packaging portfolio will gain another puzzle piece led by the substrate manufacturer.
4. New Variable: Organic Bridges and the Rise of Substrate Manufacturers
However, a new variable has emerged in the advanced packaging landscape: substrate manufacturers.
As mentioned earlier, Samsung Electro-Mechanics and Qualcomm are jointly developing "organic bridge" technology for advanced packaging of AI chips, with R&D and certification having exceeded one year. The concept of the organic bridge shares the same origin as EMIB, but the bridge material is changed from silicon to organic materials commonly used in PCBs, manufactured using substrate processes. According to the specifications disclosed by Samsung Electro-Mechanics, it achieves 5 to 7 layers of RDL, with a target line width and spacing of 1.5 to 2 microns.
Note: This image is redrawn by the editor based on a real photo of the Samsung Electro-Mechanics KPCA Show 2026 exhibition board taken according to The Elec's report. It is not an official drawing by Samsung Electro-Mechanics. The parameters are public information from the exhibition board; please refer to official releases for citations.
Compared to silicon bridges, organic material bridges have lower manufacturing costs, and this solution can bypass Intel's EMIB-related patent barriers. At this stage, the project is mainly conducting performance and reliability evaluations on FC-BGA substrates embedded with organic bridges, targeting Qualcomm's large multi-chiplet AI chips for data center scenarios. The report mentions that Qualcomm filed patent applications related to interconnect bridges as early as October 2024 and recruited organic bridge technology R&D personnel in South Korea in March of the following year.
In addition to Qualcomm, Samsung Electro-Mechanics is also simultaneously advancing joint development of organic bridge 2.1D packaging substrates with multiple customers, positioning this technology as a key expansion direction for its advanced packaging business. Driven by the current demand for AI computing chips, market demand for advanced packaging substrates and chiplet interconnect solutions continues to rise. Mainstream 2.5D packaging solutions mostly rely on silicon interposers or silicon bridges, and silicon materials bring relatively high costs. The organic bridge solution attempts to find a new balance between bandwidth and cost.
The significance of this lies not in the technology itself, but in the shift in the manufacturing link. Silicon bridges rely on wafer processes, while organic bridges rely on substrate processes—the manufacturing of bridges is shifting from wafer fabs to substrate manufacturers. For the first time, the value originally belonging to the interposer in advanced packaging has the opportunity to fall into the hands of substrate manufacturers. The "EMIB-like" collaboration between TSMC and Unimicron follows the same logic: TSMC is proactively bringing substrate manufacturers into the R&D of the bridging route. The role of substrate manufacturers is transforming from a supporting character that merely takes on packaging demands to a participant defining the route.
Conclusion
From the perspective of technology routes, advanced packaging has never been a painless substitute for Moore's Law. It merely shifts the physical limitations encountered in wafer processes to equally complex physical and chemical battlefields, such as thermal stress, coefficient of thermal expansion, micron-level alignment, and micro-bump metallurgical reactions.
In this game, no single technology route can solve all physical contradictions. All the choices made by manufacturers are merely about finding a temporary compromise between yield, cost, thermal dissipation, and computing power density.
From the perspective of the industry landscape, CoWoS will remain dominant in the short term, and TSMC's voice in advanced packaging still holds a significant proportion. However, the packaging technology routes of different players are providing customers with diverse choices.