Advanced Packaging
Following TSMC's (Taiwan Semiconductor Manufacturing Company) CoWoS yield breakthrough, the delivery bottleneck for AI chips has shifted to HBM (High Bandwidth Memory) and ABF substrates, prompting the industry to accelerate its layout of alternative solutions and glass substrates.
At the recently held OCP APAC Summit, He Jun, Vice President of Advanced Packaging Technology and Services at TSMC, revealed that CoWoS packaging with a 5.5x reticle size has now entered mass production. The yield rate during its silicon interposer processing and bonding stages has stabilized at over 98% across products for multiple AI customers, with some batches even reaching 99%. TSMC plans to implement CoWoS packaging solutions with a reticle size greater than 14x by 2029, with the 14x reticle version expected to enter mass production in 2028.
The maturation of wafer-level packaging processes has not completely alleviated the delivery pressure on AI chips. He Jun pointed out that constrained by the tight supply of High Bandwidth Memory (HBM) and ABF substrates, there is still a gap in overall delivery.
This article focuses on the new bottlenecks following the CoWoS yield breakthrough, outlining changes across three levels:
Capacity diversion. TSMC dominates the high-end CoWoS packaging capacity, while ASE, Amkor, and Samsung are absorbing spillover orders leveraging their respective technological routes.
Supply chain pressure. The capacity gap in ABF substrates and HBM has replaced the packaging and processing stage as the most critical delivery constraint.
Alternative paths and next-generation materials. Solutions such as EMIB (Embedded Multi-die Interconnect Bridge) and EFB (Elevated Fanout Bridge) are utilized to reduce the industry's reliance on the single CoWoS route; glass substrates are regarded by the industry as a technological reserve for breaking through the physical limits of organic substrates in the medium to long term.
01. Continuous Expansion of Packaging Size, Accelerated Diversion by Foundry and OSAT Giants
As monolithic dies are constrained by the physical limit of the standard reticle exposure area of approximately 858 square millimeters, splitting compute chiplets through the Chiplet architecture and integrating them with HBM stacking has become the mainstream direction for AI chips. The packaging silicon interposer area corresponding to the 5.5x reticle size has been expanded to nearly 4,700 square millimeters. Achieving a yield rate of over 98% on such a large-area silicon interposer indicates that TSMC's defect control processes in redistribution layers and microbump bonding have stabilized.
According to TSMC's roadmap, CoWoS packaging solutions with a reticle size greater than 14x will be implemented by 2029; industry estimates indicate that this specification can accommodate more than 10 compute chiplets and over 20 HBM stack modules.
In the face of the tight supply of TSMC's CoWoS capacity, other wafer foundries and OSAT leaders are competing for spillover orders in advanced packaging.
The VIPack platform and FOCoS (Fan-Out Chip on Substrate) launched by ASE are actively competing for non-core chip orders from cloud customers; Amkor signed a ten-year cooperation framework with TSMC in June this year, relying on its newly built facility in Arizona to undertake the back-end testing and final packaging processes of chips from TSMC's Phoenix fab; Samsung Electronics is leveraging its I-Cube and SAINT (3D stacking) technologies to seize orders, relying on its one-stop service of "wafer foundry + memory + advanced packaging" to serve customers with tight packaging capacity.
02. ABF Substrates and HBM Face Capacity Stress Tests
As the processing yield of silicon interposers improves, the delivery bottleneck begins to shift upstream in the supply chain, with the tight supply of high-end ABF substrates and HBM being the most prominent.
Even though NVIDIA, AMD, and large cloud service providers have locked in ABF capacity through Long-Term Agreements (LTAs) up to 2028, the market's anxiety over the shortage of high-end substrates remains unresolved. To adapt to the 5.5x and subsequent 14x ultra-large reticle specifications for CoWoS packaging, the layer count of high-end ABF substrates has been upgraded to 18-20 layers; the substrate size for the 14x reticle can reach 100×100mm. Large-size, high-layer-count substrates are highly prone to deformation after multiple rounds of hot pressing processing, which increases the difficulty of microvia alignment and drags down the yield rate of substrate manufacturers.
Facing structural gaps, global substrate manufacturers have launched a new wave of capital expenditure.
Unimicron has increased its 2026 annual capital expenditure to NT$53.7 billion, focusing on the construction of the Guangfu Phase 2 Plant and Yangmei Phase 2 and 3 Plants; Kinsus Interconnect Technology added NT$19.6 billion to build the Yangmei K6C and K6D plants and plans to seek new factory sites; Nan Ya PCB is expanding advanced capacity at the Shulin plant and upgrading the Jinxing plant, while also leasing factory space to expand supply; supply chain sources indicate that Lianneng, under Zhen Ding, is advancing the expansion of its Shenzhen facility, with rumors planning to expand to more than 7 plants by 2030.
The memory sector also faces the dual test of engineering breakthroughs and capacity ramp-up. SK Hynix is advancing the mass production of HBM3e using the Advanced-MR-MUF packaging process to maintain its market leadership; Samsung Electronics is mainly promoting the NC-TCB thermocompression bonding process to iterate its HBM product line, while SK Hynix and Micron plan to outsource the base die of HBM4 to TSMC's advanced process foundry; Micron, relying on the 1β nm process, is focusing on the high-capacity 24GB/36GB HBM3e market.
03. Chip Giants Build Alternative Paths with EMIB and EFB
Capacity constraints in advanced packaging at wafer foundries and high foundry costs have prompted chip giants and cloud providers to build 2.5D packaging alternative routes independent of CoWoS.
The EMIB route led by Intel achieves high-density interconnects by embedding micro silicon bridges inside organic substrates; by eliminating the entire silicon interposer, overall manufacturing costs can be compressed.
In addition to Intel's own processors, Microsoft's custom Maia 100 chip and Amazon's cloud chips are evaluating this solution; according to industry sources, Google's TPU team is also examining the EMIB system.
AMD CEO Lisa Su previously announced an increase in investment in Taiwan's semiconductor supply chain, building a local EFB (Elevated Fanout Bridge) 2.5D packaging ecosystem based on procurement agreements; cooperating OSATs include ASE, SPIL (Siliconware Precision Industries), and Powertech Technology. This packaging route has driven substrate manufacturers such as Unimicron, Kinsus, and Nan Ya PCB to launch specialized capacity expansion for high-end bridge substrates.
04. Glass Substrates Become the Focus of Next-Generation Material Layout
Facing the demand for ultra-high-density interconnects and ultra-large-size packaging, organic ABF substrates are constrained by the physical bottlenecks of thermal expansion mismatch and high-frequency signal loss. The industry has begun to promote the R&D and implementation of glass substrates and TGV (Through Glass Via) technologies.
Glass substrates possess an extremely low coefficient of thermal expansion, which can alleviate substrate warpage during high-temperature processing; they also have lower dielectric loss, capable of supporting ultra-high-speed signal transmission.
In July, Intel officially announced a strategic partnership with Lens Technology to jointly develop advanced packaging solutions with glass substrates tailored for AI and high-performance computing.
According to supply chain sources, TSMC is developing panel-level packaging and glass interposers relying on TGV technology. The industry estimates that it will build a process demonstration production line between 2027 and 2028.
Samsung Electro-Mechanics and Absolics, under SK, have both set up TGV pilot production facilities; Absolics aims to start small-batch pilot production by the end of 2026, while Samsung Electro-Mechanics is currently mainly conducting sample inspections for leading data center customers.
In the upstream supply chain, Corning, SCHOTT, and DNP are focusing on high-density TGV substrate raw materials; Germany's LPKF is deeply engaged in TGV laser-induced drilling and via metallization filling processes, conducting technical collaboration with major wafer foundries.
The CoWoS packaging yield crossing the 98% threshold marks that the most critical technical hurdle in advanced packaging manufacturing has been overcome. However, the delivery challenges for AI chips have not disappeared; instead, the bottleneck has shifted: from the bonding and exposure precision difficulties within TSMC's fabs to the lamination yield of substrate manufacturers, the TSV (Through-Silicon Via) capacity of memory manufacturers, and the pace of advancing glass substrate technology from the laboratory to production lines.
The first half of the advanced packaging competition compares the process limits of foundries; the second half tests the comprehensive engineering capabilities of the entire supply chain in terms of materials, precision chemicals, and equipment coordination. This trend is not limited to AI chips; in the post-Moore era, the iteration of chip performance increasingly relies on the synchronous upgrading of packaging, substrates, and memory supporting sectors.
TSMC's yield breakthrough is not the end of the industry. As packaging specifications advance from a5.5x reticle to a 14x reticle, what determines the industry's pace is no longer just the equipment utilization rate of a single TSMC fab, but whether hundreds of upstream and downstream suppliers globally can align with the industrialization timetable.
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