Author | Su Jialing
"We only have one chance."
Reflecting on the situation when starting the business in 2023, Li Zonglin, CEO of XHEART (Xin Xin Hang Tu), described it this way.
At that time, the smart driving chip market was already crowded with players, yet XHEART decided to build a chip from scratch.
NVIDIA Orin-X, with its 254 TOPS computing power and mature software ecosystem including CUDA and TensorRT, maintained its dominant position in the high-end smart driving market.
Horizon Robotics established a foothold in the domestic automaker supply chain through its BPU architecture and Journey series chips.
Automakers such as NIO, XPeng, and Li Auto invested heavily in self-developed chips, aiming to tightly integrate smart driving algorithms with underlying hardware.
On one side were chip suppliers with mature products and software ecosystems; on the other were automakers seeking to master core technologies.
The opportunities left for latecomers appeared scarce.
Even if a chip could be manufactured, how could they persuade automakers to abandon mature suppliers and re-invest in model migration, domain controller design, and full vehicle validation? For automakers, switching chips is far more complex than simply replacing a component.
However, Li Zonglin viewed 2023 as an "excellent opportunity point."
The first question facing XHEART was not how to build a chip with greater computing power, but rather why a new chip was needed when so many mature ones already existed in the market.
01. When Models Change, Chips Must Be Redesigned
"Chip developers must first clarify who the users of the chip are," said Li Zonglin.
His answer was: In the field of intelligent driving, the user is the algorithm model.
And it was precisely the change in models that opened the window for XHEART.
Past intelligent driving systems resembled a team with clear division of labor. Perception identified road conditions, prediction judged the behavior of other vehicles, and planning determined the next move.
Different small models performed their respective duties, while the chip acted like a dispatcher, assigning different types of tasks to different computing units via multi-core, heterogeneous computing methods.
But end-to-end large models are changing this division of labor. Originally relatively independent perception, prediction, and planning tasks are increasingly integrated into unified neural networks.
Especially with the widespread application of the Transformer architecture, requirements for matrix computation, data interaction, and storage access have changed.
Ren Shaoqing, head of NIO's intelligent driving, once shared that under specific computational loads, the memory bandwidth demand of Transformers could reach 8 to 70 times that of CNNs (Convolutional Neural Networks). This means that for the same amount of work, Transformers require chips to transport significantly more data.
If the model changes, the chip must also be optimized accordingly. Some previous chip architectures primarily optimized for computational loads like CNNs could run Transformers but might not allow new models to achieve optimal efficiency. Thus, this presents an opportunity for new players to bypass existing paths and design chips around next-generation models.
The actual performance of a chip in a vehicle cannot be judged solely by surface parameters. Processing speed and energy consumption in real-world tasks are mainly influenced by three factors:
First, the chip's own computing capability, known in the industry as the TOPS metric. More computing units and faster operations theoretically allow for more completed tasks.
Second, how much of these computing resources can actually be utilized. During large model execution, computing units continuously read weights, process inputs, and pass intermediate results to the next step.
Third, the efficiency with which algorithms use computing resources. Even if the hardware is powerful and computing units work continuously, inference speed will still be slowed down if the model itself contains extensive redundant calculations or if the software deployment method is inefficient.
Conversely, model optimization, operator fusion, and improvements in compilers and toolchains can enable the same hardware to perform more effective computations.
This imposes new requirements on chips. In the AI inference phase, besides ensuring sufficient computing power, large models need to shorten the data transportation path within the entire chip system, which directly impacts two things:
In terms of performance, if the chip design does not account for the characteristics of large models, data will be repeatedly transported across the chip, causing significant waiting times;
In terms of power consumption, data transportation generates substantial heat, transferring thermal pressure to the domain controller and even the entire system.
From hundreds of TOPS to thousands of TOPS, theoretical computing power continues to grow. How to make this computing power truly effective has become a problem more complex than simply adding computational resources.
Turing Award winner Jack Dongarra stated that thirty years ago, floating-point operation costs were extremely high; today, machine floating-point computing power is generally abundant, and the true bottleneck has become data transportation. A shift to new benchmarks is needed to match current architectures and measure system performance.
For automotive chips, beyond paper metrics like "TOPS/W" (computing power provided per watt of power consumption), actual performance must be evaluated:
System power consumption under target response time,
Performance and temperature changes under sustained load.
Through coordination between models, chips, and whole-vehicle thermal management, driving capabilities can operate stably across different vehicle models.
Therefore, instead of chasing along the past routes of mature manufacturers, it is better to design chips directly from future models. XHEART decided to create a general-purpose chip architecture for large models, introducing real model requirements from the architecture definition stage.
Of course, betting early on future models also implies risk.
On one hand, algorithm iteration and chip development are not synchronized. Models may undergo significant iterations every few months, while a vehicle-grade chip often takes several years from architecture definition and tape-out to mass production. By the time the chip is installed in vehicles, the originally targeted smart driving models may have gone through several rounds of iteration.
On the other hand, in the chip industry, the further into R&D, the higher the financial and human resource investment. Once tape-out is complete, changing the underlying architecture is often prohibitively expensive. For latecomers like XHEART, this is essentially a bet with little room for trial and error. This is what Li Zonglin meant by "only one chance."
XHEART's solution is to move the alignment between models and hardware forward, allowing future algorithms to be validated before chip tape-out.
The key partner here is Momenta. During the initial architecture design, XHEART relied on Momenta's judgment of algorithm trends to drive joint definition and synchronous iteration of algorithm models and chip architectures.
In this system mechanism, Momenta brings not just a ready-made model, but also computational characteristics and algorithm evolution directions from mass production lines, such as what future large models might look like and which computations consume the most resources. XHEART uses this input to independently complete chip architecture, storage bandwidth, and toolchain design.
XHEART did not choose an easier path but actively narrowed the battlefield, betting the next few years on understanding the computational needs of smart driving large models.
In the past, chips determined what models could achieve; now, models begin to determine how chips should be built.
02. Ultra-Large Cores Minimize "Wasted" Computing Paths
Identifying new computational needs requires finding the most suitable chip architecture.
Inside XHEART, there was significant disagreement regarding how to design the next-generation NPU (Neural Processing Unit).
The team evaluated multiple architectural schemes, each corresponding to different data flow structures, requiring repeated verification through performance modeling and simulation for quantitative assessment.
Ultimately, the team bet on ultra-large core NPUs, targeting the overhead of data handover.
Flexible small-core architectures increase the burden of data handover when encountering large models. Limited by single-core computing power, large models must be split into multiple sub-models for execution, leading to massive data movement and significantly reduced overall efficiency.
This is like a production line where workers are efficient, but semi-finished products need to be repeatedly sent to different workshops. What truly slows down production is the constant transit of parts.
XHEART's choice of ultra-large cores reduces exactly this overhead. The entire end-to-end large model can run completely within a single large core, allowing data to flow as much as possible through the high-speed interconnects and multi-level caches inside the large core.
X7 Ultra converts some data interactions that originally occurred between different small cores at the level of hundreds of GB/s into high-speed exchanges within the large core at the TB/s level.
Ultra-large cores reduce data handovers caused by model splitting. Specifically for each calculation step, data can travel shorter distances.
During Transformer execution, besides large-scale matrix computations, operators such as Softmax, Transpose, and Layer Norm are frequently called.
If these operations frequently access external DDR memory, data transmission may be limited by memory bandwidth, slowing down overall inference.
Therefore, XHEART made fine-grained adaptations for these operators at the hardware architecture level, allowing related data to be processed nearby whenever possible. Some operations can skip round trips to DDR, even completing at the register level.
This reduces the chip's dependence on external memory transfers, making subsequently deployed models less likely to be bottlenecked by memory bandwidth.
According to XHEART disclosures, based on real-world testing with mass-produced Transformer smart driving models, the NPU computing utilization reached 98.7%.
This means that in this test, computing units spent the vast majority of their time working rather than waiting for data.
Deploying models onto chips also involves toolchains such as compilation, quantization, and simulation.
After selecting the hardware architecture, how efficiently models are deployed and how well computing resources are utilized depends on the toolchain.
XHEART incorporated AI toolchains into considerations from the early stages of chip design:
On one hand, improving deployment efficiency for current models. Through "whole-network fusion" and "zero-copy memory technology," data latency and DDR bandwidth consumption are reduced.
On the other hand, accommodating subsequent model changes. Whether new models can be smoothly converted and deployed on older hardware architectures while maintaining efficiency determines whether automakers can continue advancing smart driving upgrades on this platform.
Current models running fast is a result of one-time adaptation.
The ability to keep up after model updates reflects the platform's sustained value. Once a chip is mass-produced, the hardware is largely fixed, but models continue to evolve. Subsequent performance improvements rely heavily on continuous releases from compilers, operator libraries, and toolchains.
Through overall software-hardware synergy, XHEART reported 700 TOPS large model computing power based on benchmark evaluations by the National Innovation Center. The 700 TOPS figure is derived from real-world mass-produced model testing, not laboratory demos.
XHEART also disclosed that under comparable large model performance testing conditions, compared to selected industry flagship products, X7 Ultra reduced memory bandwidth consumption by 80% and improved inference energy efficiency by 100%, effectively doubling energy efficiency.
For automakers, high efficiency means having the opportunity to deploy more complex models under limited hardware conditions, leaving space for future capability upgrades.
From this perspective, XHEART demonstrated not just a choice of large-core architecture, but a methodology for organizing hardware and software around real models—ensuring current large models run efficiently while guaranteeing room for adaptation and upgrade when future models change.
03. Smart Driving Chips: Performance Proven on the Road
The chip business is a scale game.
R&D, tape-out, toolchain development, and automotive-grade validation require continuous investment. After mass production, the gross margin per chip and the sustainability of shipment growth determine whether these investments can be covered.
This has also led automakers' self-developed chips to extend beyond their own vehicle models.
Ma Donghui, President of Li Auto, stated that Mach chips can be supplied externally to help amortize R&D costs; XPeng's Turing AI chip has secured a designation from Volkswagen; NIO is also seeking more partners in the automotive and embodied intelligence fields.
For XHEART, which lacks a base volume from its own vehicle manufacturing business, scale is even more critical.
However, increasing customers brings not only shipment opportunities but also diverse development requirements.
For automakers, the significance of a chip goes beyond performance parameters; it includes whether software adaptation, system validation, and full vehicle development can be completed on schedule. Switching chip platforms often means re-confirming an entire engineering workflow.
If suppliers can pre-connect key links between models, chips, and domain controllers, automakers' later-stage integration risks can potentially be reduced.
In terms of hardware integration, different vehicle models have varying requirements for interfaces, cooling, integration methods, and safety architectures. XHEART provides COB (Chip-on-Board), SiP (System in Package), and dual X7 solutions for the X7 series, allowing customers to advance development based on existing designs and reduce some repetitive work.
Algorithm adaptation faces similar issues. Customers may use external algorithms or insist on self-development. Even if both are based on Transformers, model structures, operator combinations, and deployment requirements may differ. XHEART sells SoCs independently, allowing OEMs to select chips and algorithms separately. This means using XHEART chips does not require binding to Momenta's algorithms.
Momenta provides the depth of mass-produced models, while XHEART safeguards the openness of the chip platform.
Delivery capability ensures that customers can install chips on schedule after selection. XHEART's first X7 chip went from sample return to closed-loop vehicle integration in just 17 days, whereas the industry typically takes several months.
Behind this speed is XHEART moving some problems that would originally need to be solved after sample return forward into the chip R&D stage.
Before X7 tape-out, the team conducted full-chip simulation verification with Momenta using real mass-produced large models. By checking model operation on expected architectures with data from various scenarios, they identified potential software-hardware adaptation risks as early as possible.
Simultaneously, XHEART initiated domain controller design with OEMs in advance.
Both parties began integrating and validating related components before the chip samples returned. By the time the chips arrived, models, software, and domain control systems already had a foundation for prior development.
Eight months after mass production, the X7 series has shipped over 200,000 units cumulatively, installed in 10 mass-produced vehicle models, and secured orders for over 40 vehicle models.
However, in the broader automotive chip industry, 200,000 units remains just a starting point.
XHEART needs to convert the model optimization methods accumulated through collaboration with Momenta into reusable toolchains and engineering capabilities for more customers to form true economies of scale.
As intelligent driving advances toward L3 and L4, this system will face more complex challenges.
Higher levels of autonomous driving require not only larger models but also stricter real-time performance, fault detection, and safety redundancy capabilities.
XHEART has launched reference designs for L3/L4 domain controllers based on the dual X7 architecture and has begun promoting relevant vehicle projects.
The next-generation X9 is planned for launch in 2027, targeting 3000 TOPS of large model computing power and 700GB/s of single-chip memory bandwidth.
From current mass production to next-generation products, the true barrier in the future will be the systematic ability to continuously understand models, organize computing power, and serve different automakers.
Model changes have opened an entry point for latecomers. The next round of competition in smart driving chips is shifting from comparing paper computing power to competing on who can run stronger large models with higher efficiency and more controllable costs on more mass-produced vehicles.
Three years ago, the decision based on "only one chance" has resulted in 200,000 chip shipments today, but the real major test has only just begun.