In the past few years, competition in autonomous driving chips has largely revolved around the concept of TOPS. However, as end-to-end large models gradually enter vehicle-side applications, the logic of chip competition is shifting. With model architectures, parameter scales, and computation methods continuously evolving, the traditional development mode—centered on hardware capabilities with algorithms subsequently adapted to chips—is facing new challenges. Chip manufacturers no longer need to consider only how much computing power they can provide, but rather how to design hardware around the actual computational needs of autonomous driving models. From adapting models to fit chips to having models participate in defining chips, autonomous driving computing platforms are entering a new phase of software-hardware co-design.
01. Changes in Model Architecture Are Forcing Adjustments in Chip Design
Past autonomous driving systems consisted of multiple functional modules such as perception, prediction, and planning. Different modules undertook relatively clear tasks, allowing chip manufacturers to design hardware based on the computational characteristics of these tasks. Algorithm teams then adapted models according to the chip's computing power, supported operators, and memory resources.
Under this model, chips primarily provided standardized computing resources, while algorithms sought optimal implementation methods within given hardware conditions. However, the development of end-to-end models is changing this relationship.
End-to-end autonomous driving models require comprehensive processing of camera images, vehicle motion states, and historical temporal information, using neural networks to complete environmental understanding and driving decisions. With the introduction of Transformer architectures and larger-scale models, the computational characteristics of models have also changed.
For example, the attention mechanism in Transformers requires processing information correlations across different times and positions, involving extensive matrix operations and intermediate data storage. As model scale expands and input sequences grow, requirements for computing power and data transmission efficiency increase accordingly.
This means chip design cannot consider only peak computing power; it must also understand how models actually operate. If the target model heavily uses matrix multiplication, the chip needs efficient matrix calculation capabilities. If the model involves frequent reading and writing of intermediate features, on-chip cache and memory access must be optimized. If the model employs low-precision computation, the hardware must provide corresponding support.
Different model architectures impose varying requirements on chip computing units, storage structures, and data transmission methods. Therefore, so-called "model-defined chips" do not mean algorithm teams directly decide how chips are manufactured. Instead, it means incorporating the network structure, key operators, computation precision, and data flow requirements of target models into hardware architecture design at the initial stage of chip definition.
This effectively moves part of the model adaptation work that previously occurred after chip mass production forward to the chip definition stage. SAIC Motor's layout for next-generation autonomous driving computing chips announced on October 28 reflects this direction, starting from model requirements to promote collaborative design among algorithms, chip architectures, and computing resources. However, this does not mean traditional modular autonomous driving architectures will disappear immediately. Rather, as model computational tasks become more complex, a tighter collaborative relationship between chips and algorithms is required.
02. What Kind of Chips Do Models Need?
Model-defined chips must first address the matching problem between model computational requirements and hardware resources. This involves three key aspects: computing capability, data transmission capability, and computing resource utilization. First is the match between computing architecture and model operators. Different neural network models have distinct computational characteristics.
Traditional convolutional networks and Transformer models differ in computation patterns and data access methods. If a chip optimizes only for one type of computational task, changes in model architecture may result in underutilized hardware resources. Therefore, chips must find a balance between generality and specialization.
On one hand, specialized computing units improve execution efficiency for key operators; on the other, sufficient flexibility must be retained to accommodate continuous changes in model structures and operators.
Second is memory bandwidth and data flow design. Model operation requires not only computation but also continuous reading of weights, input data, and intermediate results. When NPU computing speed increases but memory cannot provide data in time, computing units may stall, preventing actual performance from reaching theoretical peaks. This is why memory bandwidth importance has steadily increased in the era of large models.
Memory capacity determines how much data can be stored, while memory bandwidth determines how much data can be transmitted per unit of time. Both are critical for large models requiring frequent reading of model weights and intermediate features. Chip manufacturers need to optimize on-chip caches, bus architectures, and memory control strategies based on the actual memory access characteristics of target models to minimize unnecessary data movement. When announcing its next-generation computing chip layout, SAIC also mentioned improving effective utilization of computing resources through advanced memory technology, bus architecture, and on-chip cache optimization.
Third is NPU utilization and model execution efficiency. TOPS generally represents the theoretical peak computing power of a chip at specific precision levels. However, when running actual models, computing units may not consistently operate at full load.
Reasons may include dependencies between model operators, data transmission delays, or mismatches between compiler scheduling and hardware architecture.
Consequently, chips with identical nominal computing power may exhibit differences in actual inference speed and energy consumption when running the same model.
When XHEART launched the X7 Ultra, it reported that the chip achieved an NPU computing utilization rate of 98.7% in real-world tests of mass-produced autonomous driving large models, claiming an 80% reduction in memory bandwidth consumption compared to industry flagship products.
Although these data points are test results published by the enterprise, their specific effectiveness depends on model versions, computation precision, test loads, and comparison conditions. They cannot serve as universal performance conclusions for comparing different chips directly.
However, they indicate that chip competition is shifting from simply adding computing units to optimizing computing architecture, data transmission, and task scheduling around target models.
Furthermore, model quantization has become an important aspect of software-hardware co-optimization. For instance, 4-bit quantization can compress model weight storage requirements and reduce some computational overhead, but quantization does not mean all computational steps can directly adopt 4-bit precision. Different operators vary in sensitivity to precision changes, requiring calibration and validation to ensure model performance.
SAIC's proposal to promote the application of 4-bit quantization in large-parameter autonomous driving models essentially aims to reduce vehicle-side deployment costs for large models through collaboration among models, chips, and software toolchains.
It is evident that model structure determines computational requirements, which influence chip architecture, while chip computing capabilities in turn affect model deployment methods.
This bidirectional relationship is becoming a significant characteristic of next-generation autonomous driving computing platform R&D.
03. Model-Chip Collaboration Is Changing Industry Chain Relationships
Models participating in chip design changes not only hardware architecture but also cooperation modes among chip manufacturers, algorithm companies, and OEMs.
In the past, chip manufacturers primarily provided hardware platforms, algorithm companies handled model R&D and adaptation, and OEMs integrated chips, algorithms, and vehicle electronic/electrical systems.
This division of labor was relatively clear but had issues: once the chip architecture was finalized, algorithm teams began adaptation, meaning some model computational requirements might not be fully satisfied by later-stage software optimization.
If algorithm teams participate early in chip definition, they can provide model structures, key operators, and data flow requirements during the initial hardware R&D stage. Chip manufacturers can then adjust NPU architecture, cache design, and data transmission methods accordingly. Compilers, runtimes, and model deployment tools can also be developed simultaneously, reducing later adaptation costs. The collaboration between XHEART and Momenta exemplifies this co-development approach.
According to company releases, both parties initiated collaborative research on model architectures and key operators starting from the chip definition stage. However, a noteworthy question arises: does deeper binding between models and chips imply increasing difficulty in platform migration?
The answer is yes, this possibility exists.
Chips deeply optimized for specific models achieve higher computing efficiency, but heavy reliance on dedicated operators, specific compilation tools, and runtime environments may require re-adaptation and performance optimization when future models switch chip platforms. Autonomous driving model iteration speeds often exceed the cycle from chip architecture design to mass production.
Mainstream model structures today may not remain dominant in a few years. If chips are overly designed for fixed models, they face mismatches between hardware life cycles and algorithm iteration cycles.
Therefore, model-defined chips should not merely pursue extreme performance for a single model but must also consider architectural generality and scalability. While specialized hardware improves execution efficiency for key operators, adaptation space must be reserved for different model structures, computation precisions, and algorithm versions. For OEMs, participating in chip definition also holds value.
Different vehicle models have varying requirements for autonomous driving capabilities, cost, and power consumption. High-end models may require stronger model computing capabilities, while volume-focused models prioritize balancing cost and actual experience. By unifying underlying architectures to form computing platforms with different performance tiers, various model scales and vehicle positioning can be accommodated. However, whether this solution truly reduces overall vehicle development costs depends on subsequent product reuse rates, software compatibility, and actual mass production volumes.
04. Compute Competition Enters Next Stage; TOPS No Longer the Sole Answer
Expanding model scale continues to drive autonomous driving chips toward higher computing power. XHEART's announced R&D goals for the next-generation X9 include achieving 3,000 TOPS for large model computing power and a single-chip memory bandwidth target of 700 GB/s, planned for release in 2027. However, what merits more attention than the raw computing power figures is the industry's simultaneous focus on computing architecture, memory bandwidth, and model execution efficiency.
TOPS is a theoretical computing capability metric whose values relate to computation precision and statistical standards. Identical nominal computing powers across different chips do not guarantee identical actual model performance.
More importantly, autonomous driving systems do not rely solely on NPUs for all tasks.
CPUs handle control and system scheduling, GPUs or other computing units may undertake different types of computational tasks, and memory, sensor interfaces, and in-vehicle networks also impact overall system efficiency.
Meanwhile, automotive computing platforms are constrained by power consumption, heat dissipation, reliability, and cost. A chip reaching peak computing power briefly does not imply maintaining identical performance under sustained high loads. For mass-produced vehicles, sustained operational capability, system stability, and vehicle integration are equally important.
Thus, future autonomous driving chip competition must shift from single theoretical computing power comparisons to comprehensive evaluations centered on specific models and driving tasks.
Questions closer to OEM needs include: What is the actual inference latency of the same autonomous driving model on different chips? How significant are power consumption differences under identical driving tasks? Does performance degrade during sustained operation? Can existing computing platforms continue to operate efficiently after model upgrades?
From an industry perspective, autonomous driving chip competition is extending from hardware parameter rivalry to competition in model adaptation capabilities, software toolchains, and ecosystem synergy.
Chip manufacturers need to understand models, algorithm companies need to understand hardware, and OEMs must start from actual driving tasks to foster tighter R&D systems among the three.
Autonomous driving chips being defined by models does not mean computing power competition becomes irrelevant; rather, the value of computing power must now be demonstrated through models.
In the future, the true differentiator may no longer be who has larger TOPS numbers, but who can design more suitable computing architectures around model requirements, enabling models to run faster and more stably within limited vehicle-side resources, ultimately achieving scaled mass production.