[Related Companies Involved in This Article] Huawei, TSMC (Taiwan Semiconductor Manufacturing Company), SK hynix, Micron, Samsung Electronics, Intel, SJ Semiconductor, YMTC, CXMT, JCET, TFME, HT Tech, Silicon Integrity Semiconductor, ECHINT Technology, Sky Semiconductor, Fozhixin Microelectronics, Sandieji, Caihong Shares, Kaisheng Technology, Gobica, Tunghsu Optoelectronic Technology, Han's Semiconductor, DRCLaser, Jihua Laser, DeLong Laser, Woge Optoelectronic, Boxin Cheng, AEM (Anjiili Meiwei), Wuhan Xinchuangyuan, Xpeedic, Guixin Technology, Empyrean Technology, Hejian Industrial Software, Xingxin Technology, Corning, SCHOTT, Nippon Electric Glass, AGC, Ohara Optical, DISCO, Tokyo Seimitsu, TRUMPF, LPKF, PLANOPTIK, Toppan, Tecnisco, FICT, Unimicron, Kinsus Interconnect Technology, ASE, Amkor, Powertech Technology, Synopsys, Cadence, Siemens EDA, 3D Glass Solutions, Mosaic Microsystems, Applied Materials, Lam Research, etc.
I. LogicFolding and the τ Law: How 3D Stacking Shortens the Critical Path
In May 2026, Huawei publicly proposed the τ (Tau) Scaling Law. It expands the observation scale of electronic system evolution from "device geometric dimensions" to "the time required for information to complete one effective transmission." The τ here is not a specific material or a specific packaging process, but a cross-level optimization goal. The device layer needs to reduce resistance and parasitic capacitance, the circuit layer needs to shorten critical routing, the chip layer needs to adjust logic layout and data flow, and the system layer needs to reduce the waiting time for inter-chip communication and memory access. [1]
This framework is linked to Advanced Packaging because packaging has entered the critical path. The distance between chips, the position of vertical interconnects, the length of the power delivery network, and the method of heat dissipation will all change the actual latency and energy efficiency of the system. The "shortening of lateral commuting distance" embodied by LogicFolding is precisely the chip-level expression of this idea; however, it is not equivalent to TGV, nor can it be inferred that a certain glass substrate has become Huawei's established product roadmap. [1] [2]
From the perspective of the theme of this article, the core question raised by the τ Law is: Can TSV, TGV, and Hybrid Bonding truly shorten the signal, power delivery, and data access paths, while maintaining deliverability under thermal, yield, and test conditions? Therefore, evaluating Advanced Packaging cannot just look at via hole diameter or material parameters, but must look at the time, energy, and manufacturing cost of the complete path.
II. TSV, TGV, and Hybrid Bonding: How the Three Process Platforms Collaborate
TSV, TGV, and Hybrid Bonding frequently appear together in Advanced Packaging discussions, but the three solve different problems.
TSV (Through-Silicon Via) is responsible for passing through silicon dies or silicon interposers. Typical processes include deep silicon etching, insulation/barrier/seed layer deposition, copper filling, chemical mechanical polishing, wafer thinning, backside reveal, and subsequent RDL (Redistribution Layer). It is a crucial vertical pathway for HBM (High Bandwidth Memory), multi-layer silicon device stacking, and silicon interposer platforms.
TGV (Through-Glass Via) is responsible for passing through glass interposers, glass cores, or glass functional devices. Its typical chain includes laser modification or via formation, chemical etching, sidewall preparation, seed layer and copper filling, double-sided RDL, surface treatment, and inspection. Glass has high insulation and low-loss potential, and may also support larger panel form factors; however, glass brittleness, micro-cracks, metal adhesion, filling voids, handling, and the overall package thermal path must all be verified under product conditions. [12] [13] [14]
Hybrid Bonding solves the connection of adjacent wafer or die surfaces. It replaces some microbump connections with dielectric-dielectric and copper-copper direct bonding, thereby compressing the inter-layer distance and interconnect pitch. Hybrid Bonding and TSV are not naturally mutually exclusive: in HBM or logic stacking, TSV can be responsible for passing through the silicon wafer, while Hybrid Bonding is responsible for the bonding of adjacent layers. [3]
The figure reveals the true relationship among the three: both TSV and TGV include a continuous manufacturing chain of "via formation—insulation/seed layer—metallization—RDL—assembly and testing," with only the substrate and key control points being different; Hybrid Bonding, on the other hand, is located at the interface between layers. A complex system could very well adopt TSV, glass core or glass interposer, and Hybrid Bonding simultaneously. The so-called roadmap competition must be confined to the same level and the same function, and cannot be broadly written as "glass replacing silicon" or "Hybrid Bonding replacing TSV."
III. TSV Industry Chain: Division of Labor and Representative Enterprises in the Mature Silicon Platform
TSV has already formed a relatively mature industrial ecosystem. Its value is not just in manufacturing a single copper via, but in connecting wafer processing, thinning, bonding, RDL, packaging assembly, testing, and failure analysis into a repeatable platform. Table 1 synthesizes industry chain classification information and publicly available corporate data, and supplements the evidence boundaries to compare corporate division of labor, technology platforms, and industrial status in the same view.
From the perspective of industrial division of labor, the TSV ecosystem can be divided into four layers. The first layer is the middle-of-line (MOL) manufacturing capabilities such as silicon wafer via formation, insulation, and copper filling. The second layer is the silicon interposer, HBM stacking, or wafer-level packaging platform. The third layer is bonding, assembly, testing, and thermal management. The fourth layer is design rules, SI/PI (Signal Integrity/Power Integrity), thermal analysis, and customer platform collaboration. Only when the four layers form a closed loop can the single-via capability be transformed into a stable system product.
Table 1 | TSV Industry Chain and Representative Enterprises. The classification of domestic enterprises and the description of some platforms are compiled based on industry data; the status descriptions of TSMC, SK hynix, Micron, Samsung Electronics, SJ Semiconductor, YMTC, and CXMT are combined with official corporate data. R&D, roadmap, verification, and mass production in the table have different meanings.
Thus, it can be seen that international TSV competition has entered the stage of platform efficiency and customer collaboration. TSMC's advantages are reflected in the integration of interposers, assembly and testing, and customer design rules; the three major memory manufacturers put TSV, stacking, thermal management, and memory chip design in the same product platform. Domestic definitive progress mainly comes from silicon interposer platforms, wafer-level packaging, and double-wafer bonding. YMTC and CXMT should be included in the observation of the domestic memory and 3D interconnect ecosystem, but the currently publicly verifiable technical boundaries of the two are different, and they cannot be uniformly labeled as TSV/HBM mass production enterprises.
IV. TGV Industry Chain: From Glass Substrate to Packaging & Testing and EDA
The TGV industry chain is longer than just "drilling holes in glass." Upstream glass substrates determine the dielectric, thermal expansion, and processing foundations; laser modification and etching determine the via morphology and damage; metallization and RDL determine the electrical connection capability; packaging and testing integration determines large-size assembly, yield, and reliability; and EDA (Electronic Design Automation) needs to translate glass material characteristics into usable design rules. The absence of any link may keep the material advantages at the sample stage.
Table 2 | Representative Enterprises and Core Capabilities in the Domestic and International TGV Industry Chain. Compiled based on industry data and publicly available corporate information. The list of enterprises indicates industry role clues and does not equate to established customer relationships, qualification for mass production, or acquisition of specific market shares.
This table reflects that the focus of TGV competition is shifting from single-point via formation to a complete delivery chain. Glass substrate enterprises need to provide a stable material window, equipment enterprises need to control micro-cracks and via morphology, TGV processing enterprises need to connect via formation with metallization and RDL into a continuous process, and packaging and testing factories also need to solve large-size handling, alignment, inspection, and reliability. The role of EDA has therefore risen: if there is a lack of reusable material models, design rules, and failure models, it will be difficult for customers to incorporate the glass platform into mass production design.
Industry data lists Germany's PLANOPTIK AG as a professional glass substrate manufacturer covering Glass-Core-Substrates, Wafer-and-Panel-Level Packaging, and Carriers & Tools, and mentions clues of its cooperation with Intel and TSMC. This article takes it as an industry observation but does not directly regard it as a certified supply relationship; the specific scope of cooperation, project stages, and time points should still be confirmed by corporate announcements or technical documents. Similarly, the domestic industry chain list indicates that participants are increasing, but it cannot replace the verification of yield, repeat orders, and customer certification.
V. Domestic and International Industrial Progress: Mature Mass Production, Introduction Verification, and R&D Reserves
The current Advanced Packaging industry is not one roadmap sequentially replacing another, but rather three levels of maturity coexisting simultaneously. TSV has already formed scaled applications in HBM, silicon interposers, and multiple types of wafer-level packaging; Hybrid Bonding is extending from high-end logic, memory, and image sensors to more 3D integration scenarios; TGV and glass core substrates are in the parallel stages of functional device commercialization, Advanced Packaging introduction verification, and large-size platform R&D.
Table 3 | Evidentiary summary of domestic and international industrial progress. R&D, samples, customer verification, mass production preparation, mass production, and continuous shipment are different stages and should not be combined.
The biggest difference between domestic and international roadmaps is not just how small a single via can be made. International leading platforms have bound design rules, materials, equipment, assembly and testing, and customer product cycles together, so the focus of competition has shifted to capacity, thermal design, and platform iteration. The domestic advantage is the rapid increase in industry chain participants, with local supply emerging in TSV, glass materials, laser equipment, packaging and testing, and EDA; the shortcoming lies in the insufficient connectivity of cross-link data. The key to the next stage is not to add another sample picture, but to form traceable process windows, reliability data, and repeat orders.
From the perspective of the τ Law, this progress ultimately must return to system benefits. If a more complex vertical structure shortens the signal path but increases thermal resistance, failure rate, or test cost, then it has not completed "time miniaturization." The winning solution should form a verifiable overall improvement among the critical path, bandwidth, power consumption, power delivery, heat dissipation, yield, and cost of good dies.
VI. Conclusion: How the Three Processes Turn the 3D Stacking Idea of the τ Law into an Engineering System
The true requirement proposed by the τ Law for 3D stacking is not to simply increase the number of chip layers, but to shorten the time required for information to complete one effective transmission. To achieve this goal, logic layout, vertical pathways, inter-layer interfaces, and packaging carriers must be optimized together. The significant impact of TSV, TGV, and Hybrid Bonding lies precisely in the fact that they respectively implement the 3D idea of the τ Law into three engineering positions: "through silicon," "through glass," and "across layers."
TSV provides mature vertical data and power delivery channels for active silicon dies, HBM, and silicon interposers. It makes 3D stacking no longer just physical stacking, but an addressable, powerable, and testable electrical system. For LogicFolding, the significance of TSV is to transform the originally longer lateral transmission into a shorter vertical path; at the same time, it also introduces constraints of parasitic parameters, copper stress, thinning, and heat dissipation. Therefore, whether TSV can reduce τ depends on whether the critical path benefits are greater than the newly added electrical, thermal, and manufacturing costs.
Hybrid Bonding further compresses the connection distance between adjacent chip layers. Compared to interfaces relying on microbumps, it has the opportunity to reduce interconnect pitch, inter-layer height, and interface parasitics, making vertical logic partitioning closer to the high-density short paths required by LogicFolding. It does not replace TSV, but forms a 3D network of "through-silicon pathways + inter-layer interfaces" together with TSV. Its impact is not only to improve stacking density, but also includes changing chip partitioning, cache location, power delivery network, and known good die strategies.
The role of TGV on the τ Law is located at the outer packaging and system boundaries. Glass interposers or glass cores do not directly prove that Huawei's LogicFolding has adopted TGV, but their low-loss potential, large-size routing space, and tunable material characteristics provide a new carrying method for data, clock, and power paths between chiplets. After local logic achieves vertical folding through TSV and Hybrid Bonding, TGV can undertake a larger range of passive interconnects and fan-out in suitable systems, ensuring that the chip-level "short path" does not become a long path again at the packaging level. Its value still depends on whether metallization, RDL, heat dissipation, warpage, testing, and yield can meet the standards simultaneously.
Therefore, the 3D stacking pointed to by the τ Law should not be understood as the victory of a certain via or bonding technology, but as the system synergy where TSV provides the vertical skeleton, Hybrid Bonding compresses the inter-layer interface, and TGV expands the low-loss packaging network. The three together advance the idea of "shortening the path" from the logic layout to chip stacking and packaging platforms. The final judgment criterion is not how many layers are stacked, but whether the critical path is truly shortened, whether power consumption and heat are controllable, whether the structure is testable, and whether the system can be continuously delivered with a stable yield. Only when these conditions are met simultaneously can 3D stacking truly be transformed into "time miniaturization" in the sense of τ.
References:
[1] HUAWEI Presents the Tau (τ) Scaling Law, Enabling Breakthroughs in Transistor Density and System Performance https://www.huawei.com/en/news/2026/5/ieee-iscas-tau-scaling[2] Huawei’s τ Chip Was Supposed to Melt? https://arxiv.org/html/2609.04287v1[3] Hybrid Bonding: Evolving into a Foundational Technology for Improving Semiconductor Performance https://news.skhynix.com/en/tech-note-series-ep2/[4] Wafer Level System Integration of the Fifth Generation CoWoS-S with High Performance Si Interposer at 2500 mm² https://research.tsmc.com/english/research/interconnect/publish-time-2.html[5] TSMC CoWoS https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm[6] SK hynix Begins Volume Production of the World’s First 12-Layer HBM3E https://news.skhynix.com/en/sk-hynix-begins-volume-production-of-the-world-first-12-layer-hbm3e/[7] Micron HBM4 https://www.micron.com/products/memory/hbm/hbm4[8] Samsung Ships Industry-First Commercial HBM4 With Ultimate Performance for AI Computing https://news.samsung.com/global/samsung-ships-industry-first-commercial-hbm4-with-ultimate-performance-for-ai-computing[9] Expanding the Boundaries of Chip Integration Size: SJ Semiconductor Releases 3.3x Silicon-based 2.5D Packaging Technology https://www.sjsemi.com/about/22699/155287.html[10] Adopting Xtacking® Architecture, YMTC Initiates Mass Production of 64-Layer 3D NAND Flash https://www.ymtc.com/cn/news/37.html[11] CXMT Unveils LPDDR5 Product Lineup https://www.cxmt.com/en/news/info_15.html[12] Through Glass Vias https://www.agc.com/en/products/electoric/detail/tgv.html[13] Progress and Application of Through Glass Via (TGV) Technology https://www.corning.com/media/worldwide/cdt/documents/IMAPs_Corning_TGV_FINAL.pdf[14] Glass Core Substrates for Advanced Packaging https://lide.lpkf.com/en/applications/glass-core-substrates