Three years ago, the 254 TOPS compute power of a single NVIDIA Orin-X chip was still the hard metric to measure whether a car could rank among the first tier of advanced autonomous driving. Back then, if a new car from any automaker was equipped with dual Orin chips, the press release would definitely highlight the total compute power exceeding 500 TOPS (a dual-chip redundancy scheme) in bold red.
By mid-2026, the compute power race has shifted to another dimension. Li Auto's Mach M100 chip directly reached 1280 TOPS, NIO's Shenji NX9031 also exceeded 1000 TOPS, Black Sesame's A2000X similarly hit 1000 TOPS, and Tesla's AI 5 chip is even approaching 2500 TOPS.
Looking at system-level solutions from some automakers, the numbers are even more exaggerated. Li Auto's dual-chip combination can reach 2560 TOPS, BYD's tri-chip solution exceeds 2100 TOPS, and XPeng's quad-chip solution has even been stacked up to 3000 TOPS. In the discussions within the Frontier of Autonomous Driving exchange group, compute power is also a highly popular topic, and interested readers are welcome to join the conversation.
Given this trend, the compute power race in the autonomous driving field is still accelerating and running faster. However, those who have been closely following this industry may notice that the focus of automakers and chip companies has been quietly shifting. According to statistics from March 2026, NVIDIA's market share in China's passenger car autonomous driving domain controller SoC (System on Chip) market has dropped from a long-term high of over 50% to 39.4%, while the combined share of domestic suppliers has risen to 25.1%.
This change in data does not imply domestic substitution of imports; rather, it reflects a shift in the logic automakers use to select chips. Previously, the primary concern was whether the peak TOPS was large enough. Now, more people are asking: how much compute power can this chip actually deliver when running real models? What is its power consumption? Is it compatible with the algorithm framework? Can the supply be guaranteed?
In other words, once a single chip has crossed the 1000 TOPS threshold, the actual benefits of stacking higher numbers are rapidly diminishing. An increasing number of people in the industry realize that in the second half of the compute power race, victory can no longer be determined solely by who has the larger paper numbers.
01. Is There a Whole Set of Architecture Design Between Nominal Compute Power and Effective Compute Power?
Before discussing the logic of the compute power race, it is necessary to clarify a fact: the TOPS figures promoted by chip manufacturers are almost all theoretical peaks. This value is measured under ideal conditions with specific precision (such as INT8), all computing units running at full load, and no waiting for data transfer.
However, in real-world autonomous driving scenarios, the situations encountered are much more complex. Sensor data flows in continuously, and neural network models advance layer by layer, involving massive data read/write operations, cache hits, task scheduling, and synchronization overhead. The actual compute power that can be delivered might only be 60% to 70% of the nominal value, and sometimes even lower.
Take NVIDIA's Thor chip as an example. When it was first released, it was claimed to reach up to 2000 TOPS, but the actual Thor-U version delivered to automakers only has 700 TOPS. Within the same chip series, there is a threefold difference between the promotional figure and the actual usable figure. A crucial reason why automakers have begun to intensively develop their own chips is their desire to control the entire chain from algorithms to compilation and then to hardware scheduling, thereby truly converting theoretical compute power into perceptible performance improvements.
Li Auto's Mach M100 adopts an architecture called dynamic dataflow, which is completely different from the traditional instruction queue-driven mode. In traditional architectures, computing units wait for instructions to arrive before starting work, and data must be transferred back and forth between memory and computing units, wasting a large number of clock cycles in the process. In contrast, the dynamic dataflow architecture allows the data itself to carry computing tasks and flow through the internal network of the chip. Wherever there are idle computing resources, the data automatically flows there for processing, requiring almost no additional scheduling overhead.
The related paper on this design has been accepted by ISCA 2026, indicating that it has indeed been recognized at the academic level. Li Auto claims that the operational efficiency of this chip can exceed 82%. If true, under the same nominal 1000 TOPS, its actual output would be significantly higher than that of traditional architectures.
Black Sesame's A2000 series follows a similar path. Its Jiushao NPU adopts a physical-level Unique AI computing design. Multiple computing cores do not need to perform inter-core synchronization like in traditional multi-core architectures, thereby avoiding idle waste caused by waiting for synchronization signals.
XPeng also specifically emphasized the concept of effective compute power in the promotion of its Turing chip, stating that the effective compute power of a single Turing chip is roughly equivalent to 10 Orin-X chips. It is unknown whether this figure contains marketing elements, but the core message it conveys is clear: the industry is shifting its attention from mere peak TOPS to compute power utilization rate.
In the coming years, the standard for measuring whether an autonomous driving chip is good will probably no longer be how many TOPS it has, but how many effective TOPS it can stably output under typical working conditions.
02. Are Power Consumption and Cost Becoming the New Constraints?
If it were just a matter of increasing the compute power utilization rate, the problem would not be too complex. But the key is that the metric of how much effective compute power can be exchanged for every watt of power consumption and every dollar of cost is becoming increasingly critical.
In advanced autonomous driving systems based on the dual Orin-X solution, the BEV (Bird's Eye View) perception module is a major consumer of compute power. Industry technical analysis points out that the compute power occupied by this module can approach 60% of the entire system resources. This means that when the vehicle activates the urban NOA (Navigate on Autopilot) function, the system power consumption of the two Orin-X chips will significantly increase, approaching the level of 40 watts.
This power consumption level will directly affect the driving range for pure electric vehicles. Although 40 watts is not large compared to the tens of kilowatts of power required to drive the electric motor, in scenarios with low vehicle speeds and long-term urban driving, the continuous power consumption of the autonomous driving system, stacked with the cockpit and other electronic devices, means its impact on the overall vehicle energy consumption can no longer be ignored.
Besides compute power utilization rate, another key metric is cost. McKinsey predicted in an industry report that the global semiconductor market related to ADAS and autonomous driving would be approximately $5.6 billion in 2025 and expand to over $46 billion by 2035, with a compound annual growth rate of 24%. While the market is indeed growing rapidly, automakers' control over costs is now much stricter than in previous years.
Previously, automakers could stack two or four Orin chips regardless of cost to ensure compute power redundancy. Now, everyone is calculating the economic account. The procurement price of a high-compute-power chip, plus the costs of supporting PMIC (Power Management IC), thermal management, and PCB (Printed Circuit Board) design, often runs into hundreds or even thousands of dollars. This money will ultimately be reflected in the vehicle price. If spending double the money only yields a 20% to 30% actual performance improvement, this cost-effectiveness is hard to accept in the current price war environment.
Therefore, we can see that the chip selection trend in 2026 has shifted from a sole focus on performance to a comprehensive consideration of supply stability, algorithm compatibility, and energy efficiency ratio. The Chinese high-compute-power autonomous driving chip market is expected to reach a scale of 85 billion RMB this year. Faced with such a large market pie, no company will foolishly focus solely on the single metric of TOPS to make decisions.
03. Is the Memory Wall Becoming a More Intractable Bottleneck Than Compute Power?
The issue of compute power has not been completely resolved, and another more hidden problem has already surfaced: memory bandwidth and capacity.
After end-to-end models are deployed in vehicles, the number of model parameters often reaches billions or even tens of billions. Moreover, these models are no longer simply mapping from camera input to control output; they involve operations that heavily consume memory bandwidth, such as multimodal fusion, temporal modeling, and attention mechanisms.
In particular, the self-attention layer in the Transformer architecture requires a massive amount of matrix multiplication and inner product operations between different feature vectors. The intermediate results of these operations are several times larger than the weights of the model itself. Data is repeatedly transferred between computing units and memory. No matter how strong the compute power is, if the bandwidth cannot keep up, the computing units have to stop and wait for data. This is what the industry commonly refers to as the memory wall.
In its design, Black Sesame's A2000 addresses this issue with a three-tier memory architecture. The first tier is a large-capacity, high-bandwidth NPU-dedicated cache, keeping the most frequently used data as close to the computing units as possible. The second tier is an on-chip shared cache for rapid data exchange between different computing cores. The third tier is a deeply optimized DRAM bandwidth utilization mechanism, aiming to squeeze every bit of bandwidth from the external memory.
Li Auto's Mach M100 is directly equipped with 8-channel LPDDR5X, achieving a theoretical peak bandwidth of 273GB/s; BYD's Xuanji A3 has also reached the same bandwidth level. All these efforts are attempts to push the height of the memory wall a bit higher.
However, the realistic problem is that the growth rate of models is much faster than the improvement rate of bandwidth. Some predictions suggest that when autonomous driving advances to the L4 level, the memory capacity required per vehicle will exceed 300GB. Over the past three months, the prices of automotive-grade memory chips have already risen by about 180%, and the cumulative increase in the average price of DDR5 memory has reached 288%. Factoring in these two increases, the storage cost for each NEV (New Energy Vehicle) will increase by 15,000 to 20,000 RMB.
Compute power can be forcibly increased by stacking cores and raising frequencies, but the improvement of memory bandwidth and capacity is severely limited by the number of pins in physical interfaces, signal integrity, and power budget. In the post-1000 TOPS era, whoever can make smarter designs in the memory subsystem may be more competitive than those who simply stack compute power.
04. Are Algorithms Redefining Hardware in Return, Completely Changing the Rules of the Compute Power Race?
Over the past few years, autonomous driving algorithms have evolved from traditional multi-task separate models to end-to-end models, and now the industry is advancing towards VLA (Vision-Language-Action) models and world models.
Each iteration of the architecture has a fundamental impact on the demand structure for compute power. Previously, several independent CNNs (Convolutional Neural Networks) or lightweight Transformers worked independently, and compute power could be easily allocated to different tasks. However, end-to-end models integrate perception, prediction, and planning into a single large neural network. The entire forward inference process becomes an ultra-long computational graph, and a bottleneck in any intermediate link will slow down the entire system.
VLA models go a step further; they not only need to understand visual scenes but also combine language instructions to make decisions. This means the chip must simultaneously process high-dimensional visual features and discrete text tokens, making the computing mode highly irregular.
At the level of world models, many solutions have begun to adopt DiT (Diffusion Transformer) as the core architecture. The inference process of DiT involves multiple iterative denoising steps, and each iteration requires global attention on latent space features. This computing mode places extremely high demands on the support for irregular computing and dynamic dataflow. Traditionally, chips that are particularly good at matrix multiplication and have very high peak TOPS might achieve an actual utilization rate of less than 10% when running DiT.
It is precisely for this reason that leading automakers have chosen to develop their own chips almost simultaneously. They are not simply doing this to reduce costs or eliminate reliance on suppliers; more importantly, they have a clear idea of what kind of algorithm framework they will use in two to four years, whereas general-purpose chip manufacturers cannot specifically optimize for a single automaker's future algorithms in advance.
Shaoqing Ren from NIO once said in an internal exchange that in the era of large models, a 3% improvement in performance might require a tenfold increase in training data volume. If performance progress is driven solely by increasing road test fleets and collecting more physical data, it will soon hit the ceiling of cost and physical feasibility. Therefore, future competition is not just about the size of compute power; more crucially, it is about who can achieve better model performance with less compute power and less data.
Looking back at the path after 1000 TOPS from this perspective, it is actually very clear. The numbers will continue to rise; Tesla's AI 5 chip is already approaching 2500 TOPS, and XPeng's next-generation chip is rumored to break through 2000 TOPS. However, determining the winner may no longer be about this number.
The Frontier of Autonomous Driving believes that the true focal points of future competition lie in three aspects: first, whether chip architecture can innovate to maximize the value of every transistor and every watt of power consumption; second, whether the memory subsystem can feed the increasingly large appetite of large models; and finally, whether hardware design can accurately predict the form algorithms will take in three to five years.
The compute power race has not ended, but its content has completely changed.
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