Abstract: Recently, Zeng Fanchen, General Manager of the Systems and Marketing Department at Texas Instruments (TI), accepted an exclusive media interview, clearly pointing out that the inflection point for the scale deployment of AI depends on scenario definition, the balance of underlying chip metrics, and toolchains that can lower the barrier to entry. In response to the industry trend that "the end of AI is energy," TI, as a chip solution provider, focused on showcasing its "cloud-edge collaboration" technological layout. This covers the 800V DC power architecture from grid to gate, 30kW AC/DC server power supplies, 800V-to-low-voltage integrated GaN DC converters, high-speed optical module MagPack packaging, and a liquid cooling sensing fusion solution with micro-leak detection. These end-to-end solutions empower the next-generation AI data centers and edge AI ecosystem, consolidating the underlying support for AI infrastructure.
Keywords: Texas Instruments (TI); AI Scale Deployment; Cloud-Edge Collaboration; AI Infrastructure; AI Data Center; Edge AI; 800V DC Power Architecture; Grid-to-Gate; Data Center Liquid Cooling; Optical Module; TinyEngine NPU
The "Five-Layer Cake" of the AI Ecosystem and the Hardware Challenges for the Chip Foundation
"The end of AI is energy" has become a core consensus in the semiconductor and computing infrastructure fields. Zeng Fanchen, General Manager of the Systems and Marketing Department at Texas Instruments (TI), cited the widely used "five-layer cake" analogy in the industry: starting from the top layer of applications, moving downwards to models/computing power, infrastructure, and chips, while the bottom layer supporting the entire structure is energy.
Figure | Zeng Fanchen, General Manager of the Systems and Marketing Department at Texas Instruments (TI); Source: TI
Within this massive architecture, TI's core strategic positioning focuses on the fourth layer (the chip layer). Its core mission is to support the construction of the third layer, AI data center infrastructure, upwards through a broad and highly integrated portfolio of analog and digital chips, and to efficiently interface with the energy layer downwards, addressing the hardware reconstruction challenges brought about by the surging power consumption of high-computing chips (such as GPUs/ASICs).
Zeng pointed out that we are at a critical inflection point for the scale deployment of AI. Semiconductor manufacturers must overcome the physical balance of key parameters such as power consumption, latency, and memory size at the chip level, while preparing user-friendly development toolchains to truly lower the development barrier.
Data Center Power Delivery Chain: 800V Topology Architecture and Fully In-House Integrated GaN for EMI Suppression
As single-board power consumption moves towards the kilowatt level, the line loss of traditional 48V distribution buses has reached its physical limit. Data center power distribution is accelerating its evolution towards an 800V high-voltage direct-to-server architecture. However, once the safety voltage threshold is exceeded, the difficulty of transient voltage protection and dynamic isolation caused by high voltage will increase exponentially.
Addressing this industry pain point, TI showcased a full-chain high-voltage power distribution solution covering from grid to gate at the exhibition. The front end of the system adopts a 30kW AC/DC server power supply (PSU), efficiently converting the grid side to an 800V DC bus voltage, and combines it with an 800V capacitor backup unit (CBU) and a hot-swap controller to ensure hardware-level forced shutdown and dual-path backup switching in case of local anomalies.
Entering the intermediate step-down chain, the system utilizes a GaN-based 20kW step-down converter to convert the 800V high-voltage bus voltage to 6V or 12V, completing the voltage adaptation from the computer room level to the server local distribution board. Finally, through a 6V/12kA high-current multiphase buck point-of-load converter, it directly powers the processor core to meet the extremely high current transient response rate (di/dt), ensuring power supply accuracy and dynamic performance under high-load conditions.
In high-power-density designs, increasing the switching frequency to above 500kHz is a core means to compress the volume of magnetic components and achieve device miniaturization. However, high-frequency operation generates an extremely high rate of voltage change (dV/dt). This characteristic generates conducted interference currents through parasitic capacitance in the circuit, which is highly likely to trigger false operations in the control circuit and simultaneously cause electromagnetic interference (EMI) to exceed standards, restricting the stable operation of the system.
To resolve the contradiction between high-frequency performance and electromagnetic compatibility, TI relies on its fully in-house GaN technology system encompassing "process, packaging, design, and factory," directly packaging the gate driver, high-precision current/voltage sampling, and protection circuits inside the chip. Zeng revealed that this highly integrated design can minimize the physical loop generating high-frequency interference at the chip level. Coupled with the chip's built-in dynamic slew rate adjustment function, it allows engineers to find the optimal hardware balance between thermal dissipation performance and EMC (Electromagnetic Compatibility) margin.
Liquid Cooling Becomes a Necessity: From Sub-Health State Early Warning to Edge Sensing Fusion
As the power density per rack in intelligent computing centers continues to rise, traditional air cooling has approached its physical limit. The thermal bottleneck is gradually becoming a core challenge restricting the high-density and high-performance iteration of computing power. In recent years, liquid cooling and coolant distribution units (CDU) have ushered in scale deployment and explosive growth due to their efficient heat dissipation advantages. Addressing the most thorny issues for hardware engineers in the operation and maintenance of liquid cooling systems—micro-leak detection and chemical corrosion hazards—TI has built a multi-dimensional hardware defense line starting from the signal chain and thermal management architecture.
At the basic liquid leak protection level, the system first performs dynamic resistance scanning of the leak detection cable through a high-precision ADC. Relying on high-sensitivity signal acquisition capabilities, it achieves low-latency and high-precision basic liquid leak monitoring and protection. Simultaneously, chip-level temperature and humidity sensors are installed at key nodes of the liquid cooling cold plates and distribution pipelines. By capturing micro-environment mutations in real time, it forms a dual-layer redundant verification with the resistance scanning monitoring.
In terms of flow monitoring, TI introduced a non-contact, non-invasive ultrasonic sensor solution. This solution does not require destroying the original pipeline structure, and the sensor does not directly contact the coolant, fundamentally eliminating issues such as sensor structural wear and medium corrosion failure. This significantly improves the stability of flow monitoring in liquid cooling pipelines and the overall service life of the equipment, adapting to the long-term and high-intensity operation requirements of intelligent computing centers.
Furthermore, compared to the hundreds of milliseconds of delay generated by traditional liquid cooling monitoring solutions uploading data to a central host, TI has taken a breakthrough step by integrating AI capabilities down to the underlying embedded chips of the equipment, achieving microsecond-level edge sensing fusion. The terminal processor can fuse multi-dimensional analog signals such as flow rate, pressure difference, and current in real time, independently complete data analysis and fault determination, and trigger protection responses immediately, significantly improving the system's emergency response efficiency.
Supported by this architecture, the system not only possesses real-time fault protection capabilities but can also achieve refined monitoring and prediction of the equipment's sub-health state. For example, engineers can predict lubricating oil degradation or mechanical wear based on the current noise and vibration spectrum of the water pump motor, implementing active early warning and maintenance before substantial damage occurs to the hardware.
High-Speed Signal Integrity Solutions: MagPack Packaging and BAW Clock Technology
In the design of Scale-out high-speed networks and optical modules (Networking/LPO) for AI data centers, hardware engineers must cope with stringent signal jitter and thermal management challenges within extremely constrained spaces.
To optimize heat dissipation while maintaining high-frequency switching, TI has introduced MagPack 3D packaging technology.
"Unlike the traditional planar architecture that places inductors and controllers side by side, MagPack technology changes the inductors, power devices, and controllers to a vertical top-to-bottom stacked packaging. This process not only significantly reduces the board footprint but also minimizes the parasitic inductance and capacitance of the PCB traces, optimizing the system's EMI performance from the bottom up," Zeng explained.
Meanwhile, high-speed data transmission poses extremely high requirements for the phase noise of the clock reference. Utilizing MEMS (Micro-Electro-Mechanical Systems) processes, TI has developed patented BAW (Bulk Acoustic Wave) clock technology. This technology directly integrates high-Q BAW resonators inside the clock chip, comprehensively replacing traditional external quartz crystals that are susceptible to mechanical vibration and temperature drift interference. This provides robust signal integrity assurance for 800G/1.6T high-speed optical modules, significantly improving the reliability of data transmission.
The Major Trend of Cloud-Edge Collaboration: Embedded NPU Integration and Diversified Toolchain Support
Zeng emphasized in the interview that the core development of future AI lies in the combination and collaborative coexistence of cloud and edge. Large models are responsible for large-scale training and complex inference in the cloud, while the physical world, which requires ultimate real-time performance, high privacy, and has hardware limitations, must have perception and instant decision-making completed locally at the edge.
Facing the extreme demands of the edge for power consumption, Flash/RAM size, and BOM cost, TI practices the pragmatic first principles of chip design. For control scenarios where the decision logic is linear and can be determined by conventional formulas, the system will continue to use ordinary MPUs/MCUs for non-AI processing, without pursuing AI for the sake of AI. However, for complex nonlinear control, TI has comprehensively equipped its next-generation MCU plans with self-developed micro NPU hardware accelerators (such as the TinyEngine™ NPU).
When discussing whether adding an NPU would have a significant impact on chip prices, Zeng stated, "Relying on TI's in-house digital and analog core integration capabilities, coupled with powerful model quantization products and global production scale, the introduction of AI hardware cores will not lead to a substantial increase in chip selling prices. Instead, it achieves an ultimate balance of performance and cost."
At the same time, Zeng mentioned that to completely break the deadlock of "high barriers to edge AI development," TI provides three levels of toolchain support for companies with different algorithm backgrounds. For hardware teams lacking AI experience, TI provides the end-to-end GUI-based development tool Edge AI Studio, coupled with Code Composer Studio™ (CCStudio™) integrated tools to achieve plug-and-play. For customers with partial algorithm capabilities, the underlying toolchain is fully compatible with open-source tools and command-line interfaces, retaining flexible tuning space. For top-tier hardcore teams, it directly opens the underlying registers and MAC (Multiply-Accumulate) units of the NPU, releasing the chip's energy efficiency ratio and computing performance to the extreme.
Forty Years of Deep Cultivation, Building a Sustainable Intelligent World
From the PC era and the Internet era to new energy vehicles (NEVs), and now evolving to AI data centers and edge intelligence, technological waves continue to iterate. However, returning to the underlying technical essence of the physical world, it is inseparable from high-precision sampling, efficient power management, reliable interface isolation, low-latency signal chains, and embedded processing. This is precisely the solid foundation for TI to support technological innovation.
On the occasion of its 40th anniversary in China, TI has established a complete local layout in China covering manufacturing, R&D, sales, technical support, and product distribution centers. Its Systems and Marketing team has cumulatively completed thousands of customized power and signal chain hardware designs for customers to date. Facing the massive wave of cloud-edge collaboration that will explode in the next decade, relying on continuous capacity investment in self-built factories and highly integrated chip innovation, TI is becoming a crucial technical support for hardware engineers globally and in China to transform AI from blueprints into mass production and deployment.