Author | Chen Junda, Editor | Mo Ying
The competition in AI large models is entering a new magnitude. Overseas, large models with tens of trillions of parameters are gradually becoming a reality; domestically, large models with trillions of parameters are also accelerating their catch-up. To train true SOTA models, computing clusters scaling from 10,000 cards to 100,000 cards have become the standard. However, an awkward reality is: as more and more cards are stacked, the computing power truly utilized has not grown synchronously. Huawei's simulation data shows that in a 100,000-card cluster, inter-card communication may consume over 40% of the training time, and the Model Flops Utilization (MFU) is often less than 30%.
In other words, a massive amount of expensive computing power is not truly used for computation. For frontier large models with training cycles measured in months, every percentage point increase in MFU could mean a difference of several days in training time, as well as changes in computing costs ranging from tens of millions to over a hundred million CNY. To address this challenge, an increasing number of vendors are turning their attention to a new computing power organization method—the SuperNode. Unlike traditional clusters that disperse computing cards across numerous servers, a SuperNode attempts to organize thousands of cards into a logical whole through tighter interconnects, unified memory space, and lower communication latency. The recently released Ascend 960 SuperNode is precisely such an engineered SuperNode solution for the era of 100,000 cards.
01.SuperNode Becomes the Inevitable Choice Unified Memory Addressing is the Key
Since last year, "SuperNode" has become a rapidly heating concept in the field of AI computing power. Solutions such as the Huawei Ascend 910C SuperNode took the lead in sparking industry discussions. Subsequently, domestic computing power and server vendors have also successively launched related products. For a time, SuperNode has almost become synonymous with the new generation of AI computing infrastructure. At the HC2026 conference last week, Wang Tao, Vice Chairman and Rotating Chairman of Huawei, even judged that as large models advance towards the 10T parameter scale, SuperNode is the inevitable choice for AI infrastructure construction.
However, as products continue to emerge, a more fundamental question arises: what exactly is a true SuperNode? If it merely puts more servers together and connects them via high-speed networks, what is the difference between it and a traditional AI cluster? In July 2026, during the World Artificial Intelligence Conference (WAIC), the "SuperNode Definition and Practice White Paper" was officially released. This white paper was jointly led by Peng Cheng Laboratory and the Global Computing Consortium (GCC), and co-developed by 38 institutions, providing a clear definition of SuperNode at the industry level.
The white paper proposes that a SuperNode is a computing system where multiple computing nodes are tightly connected through efficient interconnect protocols and possess the capability of unified memory addressing across physical nodes, logically featuring the characteristics of "a single computer." Taking mainstream models like MoE as an example, as the number of computing units participating in the calculation continuously increases, intermediate model results need to be frequently exchanged among a large number of units. The larger the cluster scale, the more obvious the overhead caused by communication and synchronization. At this point, if computing units are merely scattered in different servers and exchange data over the network, an increase in the number of computing cards does not mean that effective computing power can increase proportionally. In other words, what a SuperNode truly changes is not simply expanding an 8-card server to 64 cards, 1,024 cards, or even 4,096 cards, but reorganizing the connection and collaboration methods among computing units, making distributed computing resources more like "a single machine" at both the hardware and software levels.
In systems conforming to this architecture, computing units within the SuperNode access a unified memory shared pool and achieve cross-physical-node access through a global address space. In contrast, data in traditional clusters often needs to rely on network protocols for transmission between different nodes. Simulation results from Huawei's Markov Laboratory show that in a 100,000-card cluster, a system composed of 4,000-card SuperNodes can achieve an MFU 2.75 times that of a traditional 8-card server cluster. Products conforming to the architecture defined by the white paper have begun to enter the stage of scaled application. As of now, over 1,000 sets of Ascend 910C SuperNodes have been deployed, and the Ascend 950 SuperNode has also entered the stage of scaled commercial use, with applications covering multiple industries such as the Internet, telecommunications operators, finance, education, and healthcare.
From standard definition to product implementation, the SuperNode is moving from an industrial concept to reality. However, as the scale of SuperNodes continues to expand, the amount of data that needs to be exchanged between cards increases sharply, and the requirements for bandwidth, latency, and reliability also rise accordingly. The engineering difficulties of interconnection begin to emerge intensively.
02.Moving the Optical Engine Closer to the Computing Power
Currently, large-scale AI clusters mainly rely on copper cables for electrical interconnection. As SerDes rates reach 224G and above, traditional electrical interconnection solutions are facing increasing pressure. The higher the rate, the more obvious the various losses in copper cables, and the more limited the signal transmission distance becomes; when thousands of high-speed copper cables are concentrated in a high-density system, cabling, heat dissipation, and maintenance also become more complex. Thus, the industry has begun to turn its attention to "light." Prior to this, optical interconnection in data centers has long relied on pluggable optical modules: as an independent device, the optical module is plugged into the panel of switching equipment or computing nodes. The signal is first transmitted along the circuit board traces to the module interface, and then electro-optical conversion is completed within the module before entering the optical fiber.
The advantage of the pluggable design lies in standardization and maintainability; a faulty module can be replaced individually, which is also the reason it has dominated data center interconnection for over two decades. However, the traditional pluggable optical module solution also has an inherent weakness: the electrical signal from the computing unit to the module needs to go through a long circuit board path. As the rate increases, the problems caused by this electrical trace become unbearable. NPO (Near-Packaged Optics) attempts to change this process. Its idea is very direct: place the optical engine at the edge of the computing unit, allowing the electrical signal to be converted into an optical signal as early as possible.
Signals that originally needed to be transmitted over long-distance electrical connections complete electro-optical conversion at a position closer to the computing card, and then complete high-speed transmission over longer distances via optical fibers. For SuperNodes, this means shortening the electrical connection distance at higher bandwidths, while reducing interconnection power consumption and latency, and alleviating cabling and heat dissipation pressure in high-density systems. Huawei's Hi-ONE is an engineering attempt on this route. Wang Tao stated that this is the industry's first mass-produced NPO product, the NPO product with the largest transmission capacity in the industry currently, and the only NPO product that implements a built-in light source.
Hi-ONE boasts a bandwidth of up to 7.2Tb/s, which comes from the integration of 36 200G lanes. A single Hi-ONE module can replace nine 800G optical modules. For a SuperNode with thousands of computing units, interconnection devices themselves are an important part of system complexity. If the number of interconnection devices can be reduced, the cabling complexity, power consumption, and potential points of failure will also decrease accordingly.
At this stage, one of the pain points faced by NPO technology is the lack of standards: after the optical engine is placed close to the computing unit, there is no unified agreement on packaging forms, interface specifications, and light source solutions. Solutions from various manufacturers are incompatible with each other, making it difficult for the industrial chain to divide labor and scale up production, resulting in high costs. At the industry standard level, Huawei proposed a suggestion for NPO standard project initiation at the global optical interconnection standards organization OIF, which received active responses from numerous industry partners. The "12.8Tb/s Electro-Optical Near-Packaged Module" standard proposal it participated in promoting has been initiated at OIF, and is expected to form an industry standard for 6.4T/12.8T near-packaged optical modules in the future.
03.Dissecting the Ascend 960 SuperNode: How 4,096 Cards Work Like a Single Computer
If the SuperNode definition answers "what is a single machine," and NPO solves "how to communicate inside the machine," then what the Ascend 960 SuperNode needs to answer is whether these two things can truly be combined into a large-scale computing system. The Ascend 960 SuperNode is built on "UnifiedBus + Hi-ONE", adopts an orthogonal architecture and full liquid cooling design, and achieves unified memory addressing through UnifiedBus, logically integrating 4,096 computing cards into a single "supercomputer."
At the specific implementation level, the Ascend 960 SuperNode uses approximately 5,500 Hi-ONEs, replacing the 48,000 800G optical modules originally needed, reducing the number of modules to about 1/9. The reduction in the number of optical modules can synchronously decrease the number of connecting devices and potential points of failure in the entire system, and also reduce the energy consumption of the interconnection itself. At the same time, the orthogonal architecture of the Ascend 960 SuperNode allows the computing boards and switching boards to be vertically orthogonal and directly interconnected. This design significantly shortens the inter-board interconnection path, resulting in lower loss and better signal integrity. Coupled with the full liquid cooling design, it makes high-density deployment of 4,096 cards possible. In terms of scale, the Ascend 960 SuperNode can be expanded to a maximum of 4,096 cards, providing 8 EFLOPS FP8 and 16 EFLOPS FP4 computing power, as well as up to 1PB of HBM capacity, with a minimum RTT latency of 2 microseconds.
Compared to the 1,024-card scale of the previous generation Ascend 950 SuperNode, the Ascend 960 increases the computing card scale of a single SuperNode by 4 times. During large model training, model weights, gradients, optimizer states, and intermediate activation values all need to be loaded into the video memory. These parameters of the Ascend 960 SuperNode mean that the model volume that a single SuperNode can accommodate has directly stepped onto a new level, and the communication overhead caused by cross-node partitioning is expected to drop significantly. According to public data, the system power consumption of the Ascend 960 SuperNode is reduced by over 550 kW, the system availability reaches 99.8%, and the system mean time between failures is doubled.
For enterprises operating 100,000-card-level clusters, these metrics will ultimately translate into improvements in their own business efficiency. Up to this point, the Scale Up problem of SuperNodes has been temporarily answered: 4,096 computing cards can be organized into a logical whole. However, it is obvious that larger-scale AI clusters cannot be completed solely by a single 4,096-card supercomputer, and new problems arise.
04.After 4,096 Cards, How to Connect the "Supercomputers"?
With the 4,096-card SuperNode, the problem to be solved for larger-scale clusters is Scale Out—that is, the interconnection between nodes. Only by crossing this step can a 100,000-card cluster truly become a reality.
This is precisely the problem that the UnifiedBus interconnection architecture attempts to solve. UnifiedBus unifies more than a dozen interconnection protocols into the UnifiedBus protocol system, reducing the conversion overhead between different protocols, and increasing the interconnection bandwidth from the hundreds of GB level to the TB level, compressing the RTT communication latency from 7 microseconds to 2 microseconds. Based on UnifiedBus, multiple Ascend 960 SuperNodes can be connected together through the UnifiedBus network or RoCE to further build SuperNode clusters.
Through two-tier CLOS four-plane networking, the maximum cluster scale supported by UnifiedBus can reach 512,000 cards; combined with multi-rail topology technology, it can support a maximum of 1 million cards in an Ascend SuperNode cluster. However, the challenges of SuperNode clusters are not limited to "connecting more." Larger-scale AI computing clusters are not a solo show for a single type of computing unit; beyond the NPU, the CPU, memory, and storage are equally important.
In the traditional system, these resources each adopt different interconnection protocols. The larger the scale, the more prominent the overhead of protocol conversion and cross-node communication. Precisely for this reason, UnifiedBus attempts to further break the boundaries between different computing resources: under this system, different subsystems such as Ascend SuperNodes, Kunpeng SuperNodes, and KV cache clusters are interconnected as equals. The CPU, NPU, memory, and storage are no longer independent resources but communicate and collaborate through a unified protocol. This demand has become more urgent as AI enters the Agent era.
During operation, an Agent may need to call models, start sandboxes, access databases, and perform vector retrieval simultaneously, continuously exchanging data among the CPU, NPU, memory, and storage. Therefore, the integration of general computing and intelligent computing has become another direction for the evolution of SuperNodes towards larger-scale infrastructure. The newly upgraded Kunpeng SuperNode is based on UnifiedBus all-optical networking, supporting a maximum of 4,096 nodes to form a 256TB unified memory pool; in Agent scenarios, the startup of hundreds of thousands of sandboxes is improved by 30 times compared to traditional server solutions, and the efficiency of complex vector retrieval of tens of billions of thousand-dimensional vectors is doubled.
From a single 4,096-card SuperNode to clusters of 512,000 or even 1 million cards, the boundaries of computing infrastructure are continuously expanding, and running through it all is the same interconnection system.
05.Conclusion: After 100,000 Cards AI Infrastructure Enters the "Systems Engineering" Era
Returning to the question at the beginning of the article: why do 100,000 cards not yield the computing power of 100,000 cards? Because as the computing scale continues to expand, what truly limits effective computing power is no longer just the computing cards themselves. Data movement, result synchronization, communication, system heat dissipation, and fault recovery—every link in the operation of the cluster is affecting the computation, and if any single link falls behind, it will drag down the efficiency of the entire "machine."
At the HC2026 conference, Wang Tao repeatedly emphasized that today's AI infrastructure competition has progressed to a complex, multi-disciplinary stage of systems engineering. In this contest, Huawei's comprehensive advantages in "computing + communication" are concentrated: from NPU to SuperNode, from optical engines to unified interconnection protocols, every layer points to the same goal—making computing power truly utilized.