The global semiconductor industry is entering an unprecedented super-growth cycle, with the market size surpassing the trillion-dollar mark. In this profound transformation triggered by the explosion of AI computing power, the slowdown of Moore's Law has shifted the main battlefield of technological competition from "process miniaturization" to "system integration," and from single chips to full-chain collaboration from "chip to system."
On October 30, the 2026 Xpeedic User Ecosystem Conference, themed "Chips Leap into Systems, Intelligence Masters Change," was held in Shanghai. Over a thousand representatives from upstream and downstream industry leaders and academia gathered to engage in in-depth discussions around STCO (System Technology Co-Optimization), system-level EDA, and AI for EDA.
Image source: Xpeedic
The conference sent a clear signal to the industry: Computing power competition is no longer determined by single-chip performance; system-level collaboration and the deep integration of AI agents are fundamentally changing engineering design methodologies.
New Metrics for Computing Power
In the PC and mobile internet era, the industry pursued extreme single-chip metrics (such as PPA, MIPS). However, in the AI era, the surge in large model training and inference workloads has evolved the smallest unit of computation into a rack, or even an entire AI factory.
Dr. Ling Feng, Chairman of Xpeedic, pointed out that the metrics for measuring computing power have undergone an essential change, shifting to Token per second per watt and TCO (Total Cost of Ownership). To meet these new metrics, any "local optimum" in a single link can no longer guarantee a "system optimum."
The computing power performance of AI infrastructure is severely constrained by the "barrel effect" across two dimensions:
- Horizontal Dimension Collaboration: From underlying chips, advanced packaging, PCB boards, to complete racks and supernode systems, if any level in the chain falls behind, even powerful chips cannot perform effectively.
- Vertical Dimension Balance: The four core elements—computing power, storage power, transmission power, and power supply—are strongly coupled. Pursuing extreme computing density leads to thermal and power walls (power bottlenecks); insufficient storage bandwidth or slow data transfer (storage and transmission bottlenecks) also results in idle computing power.
Based on this unavoidable engineering reality, STCO (System Technology Co-Optimization) has accelerated from a concept to an indispensable engineering capability.
Industry Pain Points and the Core Value of System-Level Simulation
During the roundtable forum at the conference, experts from five key links in the hardware supply chain collectively confirmed the urgency of system collaboration from their respective industrial positions.
In the computing chip segment, experts from MetaX noted that single-chip optimization is approaching process limits. Blindly pursuing high computing density leads to insufficient local heat dissipation, triggering electro-thermal coupling issues that prevent chips from achieving design targets due to high temperatures. Therefore, boundaries of industry chain cooperation are blurring; chip design must consider packaging, heat dissipation, and server form factors upfront, making cross-layer trade-offs.
In the high-bandwidth memory field, experts from Longsys emphasized that storage is not merely about providing data; storage energy efficiency and bandwidth are now inversely constraining wafer architecture and advanced packaging choices. Computing and storage are not independent modules; the industry must move towards STCO to completely eliminate data silos between toolchains.
Regarding high-speed interconnects and complete systems, experts from Luxshare Precision mentioned that as rates advance to 224G/448G, rising temperatures increase cable attenuation. If impedance mismatches occur, the system bit error rate degrades exponentially. Previously, lacking system-level co-simulation, problems were often exposed only during final system testing, where a single design modification involving molds and equipment could cost CNY 30 million to 50 million.
In terms of advanced packaging and 3DIC, experts from XMC pointed out that after three-dimensional integrated stacking, discovering electrical, thermal, and stress multi-physics issues only after tape-out requires redoing the entire design, which is costly. This demands that advanced packaging significantly front-load system simulation, using multi-physics co-simulation to quantitatively describe and predict issues in the early design stages.
In the power and device segment, experts from Murata stated that the surge in AI chip power (e.g., 800V DC racks) leads to excessively high layout density. While small component size and high capacitance look good on single-point metrics, they may cause overall overheating when placed in a system. Power delivery is no longer just back-end system design; it must evolve from points and lines to "planes," comprehensively optimizing the Power Delivery Network (PDN) through tight alignment of EDA simulation and chip-side design.
During the media interview session, Dr. Dai Wenliang, President of Xpeedic, used the currently popular CPO (Co-Packaged Optics) technology as an example: "Packaging brings optical engines and compute chips together, bringing heat along with them. As heat rises, the wavelength of silicon photonics modules drifts; as wavelengths drift, link budgets and bit error rates deteriorate. After working on CPO for some time, people found this path difficult because optical engines and compute chips sealed together make thermal crosstalk hard to solve, and yield risks are concentrated on the most expensive die. Consequently, there is a shift towards pluggable solutions—splitting one channel into eight, creating pluggable optical modules. The logic is simple: if CPO fails, you lose the compute chip and HBM, which is too expensive; with pluggables, you simply replace the failed module, keeping costs manageable." This case demonstrates that chip design must abandon blind pursuit of single-point extremes and instead perform dynamic Trade-offs at the system level.
From EDA for AI to AI for EDA
Facing complex system-level design spaces, traditional standalone tools and serial design flows are unable to provide support, and manual exploration has reached its cognitive limit. As an EDA company labeled "system-native," Xpeedic officially released EDA2027 at the conference, showcasing its efforts in reconstructing intelligent design from chip to system.
Its technical solutions focus on three main aspects:
- Agent Level: China's First Super Intelligent Agent Platform Truly Implemented in Engineering Flows
This platform breaks down the traditional silos of library building, design, and simulation teams. A top-level large model "brain" uniformly understands natural language requirements and orchestrates multiple underlying multi-agents to collaboratively execute tasks.
- Chiplet Level (Advanced Packaging Agent): Collaboratively optimizes architecture and physical implementation in post-Moore scenarios. It automatically generates chiplet layouts and communication spacing, seamlessly invoking the Metis platform to complete electrical, thermal, and mechanical coupling Signoff, increasing design iteration efficiency by 4 times and reducing manual time by 80%.
- Board Level (PCB Agent): Lenovo's Chief Engineer demonstrated a real-world case jointly developed with Xpeedic using EDA Agent 2.0. For high-density AI PC designs, the agent automatically parses datasheets, builds libraries, completes routing with 100% connectivity for LPDDR5X, and automatically outputs simulation reports including eye diagrams and inter-symbol interference. This workflow astonishingly increased design iteration efficiency by 5 times and reduced manual operations by 90%.
- System Level (System Simulation Agent): Achieves cross-layer one-time modeling and rapid coupling analysis of electricity, magnetism, heat, fluid, and structure on a unified platform.
- Physics AI (Trusted Physical Intelligence Base XAI)
The core difficulty of introducing AI into EDA lies in avoiding machine-generated "hallucinations" and ensuring 100% reliability for tape-out and manufacturing.
To address this, Dr. Ling Feng noted that Xpeedic's XAI platform deeply binds AI surrogate models with multi-physics engine algorithms accumulated over 16 years (such as Finite Element Method, Method of Moments solvers). All AI training data is generated under physically constrained boundary conditions, achieving second-level real-time prediction and optimization, with prediction accuracy errors controlled within 3% compared to true multi-physics simulations.
- Disruptive Acceleration via GPU Computing Infrastructure
To resolve the "inability to compute" bottleneck in billion-scale ultra-large complex scenarios, Xpeedic introduced underlying solvers to the GPU platform and adapted them for CUDA for the first time.
Dr. Ling Feng revealed that the new version of tools achieved a 10x to 20x speed leap in core multi-physics products. PI solution analysis shortened from hours to minutes, while fluid solving and electromagnetic FDTD algorithms achieved more than tenfold acceleration. Combined with "near-infinite" distributed hard drive solving technology, this makes one-time convergence of larger scale system simulations a reality.
Conclusion
Under the vision of the "15th Five-Year Plan" industrial planning, advanced packaging, multi-chip integration, and EDA have been listed as priorities for national industrial foundation capabilities. AI is profoundly changing the paradigm for measuring computing power, while the intertwining of STCO and AI is partially bridging data silos across the upstream and downstream supply chain.