As computing power triples every two years while interconnect bandwidth increases by only 1.4 times, this divergence, known as the "Bandwidth Wall," is capping the expansion of AI. The CPO technology roadmap published in Nature Electronics by SK hynix in collaboration with five top global universities provides a systematic breakthrough solution—extending optical interconnects from between switching chips to memory interfaces.
1. Market Shock Triggered by a Single Paper
On August 20, SK hynix, in collaboration with the University of Virginia, MIT, the University of Illinois at Urbana-Champaign, Nanyang Technological University, and Yonsei University, published a paper titled "Co-Packaged Optics for High-Performance Computing and Artificial Intelligence" in the top-tier journal Nature Electronics (DOI: 10.1038/s41928-026-01681-6).
This marks the first time SK hynix has publicly disclosed a system-level technology blueprint for AI interconnects in a journal of this caliber. The corresponding authors of the paper are Seunghoon Hong, Head of the AI Infrastructure Team at SK hynix, and Kyusang Lee, Professor at the University of Virginia.
On the same day, catalyzed by the release of the CPO roadmap and a 40 trillion KRW share buyback plan, SK hynix's stock price in South Korea surged 12.73% at closing, reaching 1.691 million KRW.
2. The Bandwidth Wall: From Memory Bottleneck to System Bottleneck
In the era of generative AI, HBM has resolved the memory bottleneck within AI accelerator packages. By stacking DRAM chips via TSVs (Through-Silicon Vias), HBM has pushed in-package memory bandwidth to over 1.2 Tb/s (HBM3E). However, when thousands of GPUs and HBMs form ultra-large-scale clusters, a new bottleneck emerges at the level of inter-system data transmission.
The paper highlights a critical data gap: computing performance grows by approximately 3 times every two years, while interconnect bandwidth increases by only 1.4 times.
This divergence is referred to as the "Bandwidth Wall." Traditional copper wire interconnects suffer from exacerbated signal attenuation as data rates increase and distances extend, necessitating additional equalization circuits for compensation, which leads to higher power consumption and increased latency. The triple constraint of "distance-rate-power" in copper interconnects has become the physical ceiling for scaling ultra-large-scale AI clusters.
Professor Kyusang Lee from the University of Virginia stated directly, "Even if the performance of computing chips improves, if the data transmission capability between chips cannot keep up, the overall system performance will still not increase. Breaking free from physically constrained copper wiring and switching to optical data transmission is the most viable scaling path."
3. CPO Technology Path: From 2D to 3D Heterogeneous Integration
The core concept of CPO (Co-Packaged Optics) is to integrate optical transceivers and processors within the same package, minimizing the transmission distance of high-speed electrical signals, with the remaining links handled by optical signals. The paper defines the technical value of CPO from three dimensions:
Bandwidth density: The cross-section of optical waveguides is much smaller than that of copper wires, allowing more channels per unit area;
Energy efficiency-distance characteristics: Optical signal transmission loss grows extremely slowly with distance, offering significant energy efficiency advantages in long-distance scenarios;
Signal integrity: Optical signals are immune to electromagnetic interference, providing clear advantages in signal integrity during high-speed parallel transmission.
The paper systematically reviews the three-stage evolution of CPO packaging architectures:
The 2.5D stage is the current focus of industrialization, integrating optical engines and switching ASICs/GPUs within the same package via a silicon interposer, reducing the electrical signal path from tens of centimeters to the millimeter level. 3D heterogeneous integration, on the other hand, requires solving engineering challenges such as wafer-level yield in hybrid bonding and coefficient of thermal expansion (CTE) matching.
The paper sets clear technical targets for next-generation AI infrastructure: single-node bandwidth exceeding 100 Tb/s, energy consumption below 1 pJ/bit, and inter-chip latency below 10 nanoseconds.
4. Extending Optical Interconnects to Memory Interfaces
The most forward-looking part of the paper is the proposal of the "Optics-Centric Architecture."
In the current architecture, electrical signals are still used to connect HBM and GPUs, and physical space constraints limit the number of HBM stacks and interconnects that can be integrated within a package. The Optics-Centric Architecture directly connects the computing resource pool and the memory resource pool with optical signals via a photonic interposer, bypassing physical space constraints.
Its core value lies in "memory pooling," meaning multiple accelerators can share a memory pool far larger than what a single package can accommodate, so the growth in AI model scale is no longer limited by the number of HBM stacks in a single GPU package.
Professor Lee pointed out, "By extending optical interconnects to memory, we can bypass the physical constraints around computing chips and break through the upper limits of memory capacity and the number of interconnects. Multiple accelerators sharing a massive memory pool provide greater flexibility for scaling up AI models."
However, realizing this concept still requires addressing multiple challenges, including low-power optical device integration, memory coherence protocol adaptation, and reliability engineering, making it a medium- to long-term research goal.
5. Four Parallel Paths: Mass Production First and Roadmap Evangelism
Participants in the CPO track can be divided into four parallel advancement paths:
System Side — NVIDIA Leads with Mass Production
On August 14, NVIDIA announced the full mass production of Spectrum-X Ethernet Photonics, the world's first 200G/lane CPO Ethernet switch system. Equipped with the Spectrum-6 switching chip, it delivers a single-chip bandwidth of 102.4 Tb/s, double that of the previous generation. The number of lasers is reduced by 75%, power consumption is lowered by 80%, mean time between failures (MTBF) is improved by 10 times, and optical loss is reduced from 22dB to 4dB.
Chip Side — Broadcom Advances Deployment
Broadcom's Tomahawk 6-Davisson CPO switch also achieves a single-chip switching capacity of 102.4 Tbps. It utilizes TSMC's (Taiwan Semiconductor Manufacturing Company) COUPE technology to directly stack the photonic engine on the switching silicon and has been deployed by multiple cloud providers.
Foundry Side — TSMC's COUPE Roadmap
TSMC's COUPE silicon photonics integration platform, specifically built for CPO, is advancing in three stages. The third stage plans to directly integrate 12.8 Tbps optical engines into the processor package, aiming for a 5x improvement in energy efficiency and a 20x reduction in latency.
Memory Side — SK hynix's Roadmap Evangelism
SK hynix enters the CPO field as a memory manufacturer with a unique positioning—it does not manufacture CPO switches but proposes a system-level roadmap for extending optical interconnects to memory interfaces from the perspective of HBM memory, filling the gap of the "memory side" in current CPO discussions.
CPO is not merely an upgrade of a single component but a system-level co-design across four dimensions: memory devices, controllers, optical devices, and packaging. SK hynix's role is evolving from a "single product supplier" to a "system-level partner"—the scaling demands of customers' AI systems have surpassed the performance scope of a single HBM product, requiring the co-design of memory, interconnect, and packaging solutions at the system architecture level.
6. Conclusion
NVIDIA's Spectrum-X has taken the lead in mass production but focuses on the switching side, while SK hynix's paper fills the gap in the memory-side CPO roadmap; the two are more likely to be complementary advancements at different levels of AI infrastructure.
As the divergence between the growth curves of computing power and interconnect bandwidth continues to widen, "optics replacing copper" is no longer a choice but the answer dictated by the laws of physics. With the market growth forecast for CPO rising from $100 million to $39 billion, a fundamental reconstruction of the underlying AI infrastructure is moving from academic papers to production lines.
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