[Related Companies Mentioned in This Article: TSMC (Taiwan Semiconductor Manufacturing Company), Samsung, Tower, GlobalFoundries (GF), SMIC (Semiconductor Manufacturing International Corporation), Synopsys, Cadence, Xiaoyao Technology, Silicore Technology, NanZhi Optoelectronics, Shanghai Industrial Technology Research Institute (SITRI)]
Tape-out Difficulty Comparable to Launching a Rocket
It is well known that wafer tape-out has always been astonishingly expensive. Although the prices vary for wafers with different process nodes and testing requirements, tens of thousands to hundreds of thousands of dollars must still be spent in hard cash, with advanced process nodes being even more costly. The tape-out price for silicon photonics is even more staggering; a single tape-out involving photomasks, process, and cycle costs starts at the million-dollar level. From the layout to the foundry's process control side, running through the entire process step by step, and finally reaching the OSAT (Outsourced Semiconductor Assembly and Test) facility for packaging and testing, the entire cycle often takes several months. Whether it is unreasonable waveguide design, coupling loss ratios higher than expected, or other complex issues intertwined with optics, electronics, and thermal dissipation, any of these will cause your money to be burned all over again.
An industry insider once commented that for electronic chip design, simply using the PDK provided by the foundry can build a presentable product. Currently, the technical bottlenecks are basically stuck at the advanced process nodes and mass production yield rates. In contrast, silicon photonics is entirely at the process nodes of tens of nanometers to hundreds of nanometers from over a decade ago. The results run by EDA tools require tape-out verification to obtain actual results before knowing whether the simulation results are correct. For silicon photonics chips to achieve mass production, the design phase must consider not only the complex issues of traditional electronic chips, such as signal integrity, heterogeneous and hybrid integration, thermal dissipation, and power consumption, but also the overlay of interconnect material selection, differences in bonding processes, thermal stress distribution, and different stacking directions. All these will lead to fundamental changes in physical implementation and simulation algorithms. If tape-out for electronic chips is like building a car, tape-out for silicon photonics chips is more like building a rocket.
General workflow of PDK and tape-out (Image source: Shenxinmeng)
Silicon photonics chip design also faces many more photonics challenges than electronic chips: silicon cannot emit light and requires InP (Indium Phosphide) as the light source material, fiber array structure alignment, and optical waveguide loss. These component-level challenges are fundamental principle issues for designers, which can be resolved by spending time on them. However, whether the designed product can be manufactured, how to manufacture it, and what the resulting parameters will be, are information that the foundry needs to provide. The PDK (Process Design Kit) is exactly such a manual, detailing how to do it and what the effects will be in a format that designers can understand.
Silicon Photonics PDK + EDA: The True Vital Key
The PDK for silicon photonics is more complex than that for electronics. Taking Tower as an example: Tower is currently a leading silicon photonics foundry in the industry. Its officially released PDK covers all process modules, including waveguide patterning, modulator integration, photodetector formation, metal interconnection, thermal phase control heaters, and wafer-level testing. The PDK provided by the foundry contains a key piece of information—guarantees. For complex systems, every component must be precise enough, and the error must be small enough, so that the final actual product closely resembles the initial design. All components in the PDK are standard model components manufactured through actual processes, and each parameter is a real physical quantity measured in practice, not the theoretical value of the component. In this way, fabless companies can ensure as much as possible during design that the final product after tape-out is exactly what they want.
SOI wafer to silicon Photonics PIC (Image source: Xiaoyao Technology)
Looking closely, the PDK is generally divided into a three-layer structure, each of which is crucial:
￮ Component Library: The core of the PDK is the components actually manufactured by the foundry. Each one is a standard component that the Fab has run, verified for yield and performance. Designers can directly take waveguides, multimode interference couplers, grating couplers, or fiber couplers from the library without designing them from scratch. Using them directly is the best tool for design.
￮ Design Rule Check (DRC): The PDK includes extremely detailed check rules, such as line width, line spacing, minimum bending angle, and attribute definitions for each layer. DRC defines a set of physical world rule red lines. The system will comprehensively check every detail when your design is completed, ensuring as much as possible that there are no design flaws.
￮ Compact Model Simulation: After designers build devices using all PDK components and follow the DRC, the system needs to perform complex simulations to predict system performance. Photonics signals in the system follow S-parameters (information describing the amplitude, phase, and frequency of optical signals). By calculating the results under different interface conditions such as temperature, voltage, and line width, it can be seen whether the desired device performance is finally achieved.
This set of PDK is the same for electronics, but the electronics PDK has accumulated nearly thirty years of experience. The pitfalls that needed to be stepped on have already been navigated. Silicon photonics started later, and optics is inherently more difficult than electronics. In digital circuits, whether the line width is slightly wider or narrower, as long as the signal is not distorted, there is generally no problem. However, if the waveguide line width differs by a few nanometers, the accumulated phase of the optical signal will change, and the entire interference signal will have a risk of distortion. At the same time, optical devices have an additional optical part compared to electrical devices. Both are affected by electric fields, thermal fields, interconnections, stacking, and many other factors. In particular, in optical responses, modulators suffer from wavelength drift caused by temperature.
Additionally, on the EDA side, a Fab's PDK needs to be bound to an EDA tool suite, such as Synopsys's OptoCompiler, Cadence, and Keysight's ADS. Once a design company chooses a specific Fab for development, the entire design flow is built upon it. From the NTO (New Tape-Out) to the MP (Mass Production) stage, the entire team is firmly bound to the Fab's model library, device cells, and simulation experience. In other words, whichever EDA integrates a Fab's PDK most completely, practitioners will tend to prefer that EDA.
Overview of Industry PDK + EDA Vendors
Silicon photonics foundry giant Tower has integrated its own PDK into the Luceda IPKISS software, forming an ecosystem where using the OpenLight PDK for drawing can directly connect to Tower's process tape-out. GlobalFoundries (GF) has developed its own Fotonix silicon photonics platform. Fotonix is also the most recognized, most complete, and most mature silicon photonics PDK platform in the industry. Broadcom, NVIDIA, and Cisco are all major customers of this Fab. Samsung has also launched its own 300-mm silicon photonics PDK platform based on the 300mm (12-inch) SOI CMOS process. TSMC's COUPE starts from the system level, integrating a series of silicon-based light emission for optical signals, signal modulation, couplers, waveguides, and optical engine light emission into a single package. Compared with traditional device-level PDKs, it adds 3D stacking, array reflection, and wafer-level optoelectronic testing. TSMC also holds over fifty core patents in silicon photonics, almost covering the "life to death" of optical signals, creating a very deep moat.
Overview of Silicon Photonics Foundry PDKs (Image source: SST)
Similarly, a group of startup EDA companies and silicon photonics PDK platforms have also emerged in China:
￮ Xiaoyao Technology: Focuses on the full-process independent EDA software development for optoelectronic integrated circuits (PIC) and special processes. Its core product, PIC Studio, has opened up a complete closed loop from schematic design, optoelectronic mixed simulation to automatic layout and routing of the layout and physical verification. It possesses excellent multi-solver compatibility and localized customization capabilities, making it a leader in domestic photonic integrated circuit design EDA software.
￮ Silicore Technology: Based on the fields of 2.5D/3D stacking (Chiplet) and advanced packaging, it proposes a unique "EDA+" solution and successfully creates the "3Sheng Integration Platform". It breaks through the limitations of traditional 2D design, providing full-chain collaborative capabilities covering architecture exploration, 3D cross-chiplet physical verification (DRC/LVS), electro-thermal coupling, and signal integrity (SI/PI) simulation. It specifically solves the large-scale heterogeneous integration challenges of complex computing power and HBM (High Bandwidth Memory) chips.
￮ NanZhi Optoelectronics: Focuses on cutting-edge heterogeneous integration material systems such as thin-film lithium niobate (TFLN) and thin-film lithium tantalate (TFLT). By developing proprietary PDKs for ultra-high bandwidth (>50GHz) and low-loss devices, it deeply binds model design with its own pilot tape-out line, constructing an efficient closed-loop platform of "PDK R&D - simulation verification - foundry production".
￮ Shanghai Industrial Technology Research Institute (SITRI): As an industrial-grade R&D and pilot platform in the "More than Moore" and silicon-based optoelectronics fields, it has created a high-precision standard PDC/PDK system (covering processes such as 180nm/90nm SOI) based on real mass production data from 8/12-inch wafer lines. It can seamlessly integrate with mainstream international optoelectronic EDA software, providing strong chip design and MPW (Multi-Project Wafer) tape-out support for enterprises in optical communication and optical computing.
￮ Jiufengshan Laboratory: Located in Wuhan, the Jiufengshan Laboratory is a compound semiconductor and silicon photonics heterogeneous integration platform. It focuses on the R&D of proprietary PDKs for silicon-based III-V heterogeneous integration, high-bandwidth modulators, and optoelectronic fusion integration, based on the architectural design of a new generation of high-speed CPO (Co-Packaged Optics) and NPO (Near-Package Optics) optoelectronic chips.
Overview of Domestic Silicon Photonics PDK and EDA Vendors (Image source: Shenxinmeng)
In addition to commercialized EDA and PDK software, the industry is also continuously developing open-source, verifiable, and cross-Fab portable device model libraries. For example, the team from Yokohama National University created an open-source Verilog-A photonic model library, verifying the signal rate all the way to 64 Gbps, and making all details public, striving to break the industry pattern of enterprise closed-source PDKs.
Conclusion
As the core guarantee for silicon photonics design, which is ten times more difficult than electronic design, the PDK is the foundation for chips to move from the laboratory to scaled mass production. Without a solid foundation, no matter how good the chip design is, it is merely a castle in the air. The coordinated development of PDK and EDA software is the most vital key in this smokeless technological war.
The illustrations in the article are generated by generative AI
References:
"Why is Silicon Photonics So Difficult to Design? The Answer is Hidden in a Box Called PDK"
"Silicore Technology: Defining the New Paradigm of 'EDA+', Breaking Through the 'No Man's Land' of Advanced Packaging Design"